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lucasdemarchirodrigovivi
lucasdemarchi
authored and
rodrigovivi
committed
drm/i915/icl: Introduce new macros to get combophy registers
combo-phy register instances are at same offset from base for each combo-phy port, i.e. Port A base offset: 0x16200 Port B base offset: 0x6C000 All the other addresses for both ports can be derived by calculating offset to these base addresses. PORT_CL_DW_OFFSET 0x0 PORT_CL_DW<x> 0 + x * 4 PORT_COMP_OFFSET 0x100 PORT_COMP_DW<x> 0x100 + x * 4 PORT_PCS_AUX_OFFSET 0x300 PORT_PCS_GRP_OFFSET 0x600 PORT_PCS_LN<y>_OFFSET 0x800 + y * 0x100 PORT_TX_AUX_OFFSET 0x380 PORT_TX_GRP_OFFSET 0x680 PORT_TX_LN<y>_OFFSET 0x880 + y * 0x100 And inside each PORT_TX_[AUX|GRP|LN] we add `dw * 4`. Based on original patch by Mahesh Kumar <mahesh1.kumar@intel.com>. v2: make port, dw and ln arguments follow the order in register's name Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181016023517.8576-1-lucas.demarchi@intel.com
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‎drivers/gpu/drm/i915/i915_reg.h

Lines changed: 59 additions & 104 deletions
Original file line numberDiff line numberDiff line change
@@ -1658,20 +1658,21 @@ enum i915_power_well_id {
16581658
/*
16591659
* CNL/ICL Port/COMBO-PHY Registers
16601660
*/
1661+
#define _ICL_COMBOPHY_A 0x162000
1662+
#define _ICL_COMBOPHY_B 0x6C000
1663+
#define _ICL_COMBOPHY(port) _PICK(port, _ICL_COMBOPHY_A, \
1664+
_ICL_COMBOPHY_B)
1665+
16611666
/* CNL/ICL Port CL_DW registers */
1662-
#define CNL_PORT_CL1CM_DW5 _MMIO(0x162014)
1663-
#define _ICL_PORT_CL_DW5_A 0x162014
1664-
#define _ICL_PORT_CL_DW5_B 0x6C014
1665-
#define ICL_PORT_CL_DW5(port) _MMIO_PORT(port, _ICL_PORT_CL_DW5_A, \
1666-
_ICL_PORT_CL_DW5_B)
1667+
#define _ICL_PORT_CL_DW(dw, port) (_ICL_COMBOPHY(port) + \
1668+
4 * (dw))
1669+
1670+
#define CNL_PORT_CL1CM_DW5 _MMIO(0x162014)
1671+
#define ICL_PORT_CL_DW5(port) _MMIO(_ICL_PORT_CL_DW(5, port))
16671672
#define CL_POWER_DOWN_ENABLE (1 << 4)
16681673
#define SUS_CLOCK_CONFIG (3 << 0)
16691674

1670-
#define _CNL_PORT_CL_DW10_A 0x162028
1671-
#define _ICL_PORT_CL_DW10_B 0x6c028
1672-
#define ICL_PORT_CL_DW10(port) _MMIO_PORT(port, \
1673-
_CNL_PORT_CL_DW10_A, \
1674-
_ICL_PORT_CL_DW10_B)
1675+
#define ICL_PORT_CL_DW10(port) _MMIO(_ICL_PORT_CL_DW(10, port))
16751676
#define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25)
16761677
#define PG_SEQ_DELAY_OVERRIDE_SHIFT 25
16771678
#define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24)
@@ -1687,31 +1688,23 @@ enum i915_power_well_id {
16871688
#define PWR_DOWN_LN_MASK (0xf << 4)
16881689
#define PWR_DOWN_LN_SHIFT 4
16891690

1690-
#define _ICL_PORT_CL_DW12_A 0x162030
1691-
#define _ICL_PORT_CL_DW12_B 0x6C030
1691+
#define ICL_PORT_CL_DW12(port) _MMIO(_ICL_PORT_CL_DW(12, port))
16921692
#define ICL_LANE_ENABLE_AUX (1 << 0)
1693-
#define ICL_PORT_CL_DW12(port) _MMIO_PORT((port), \
1694-
_ICL_PORT_CL_DW12_A, \
1695-
_ICL_PORT_CL_DW12_B)
16961693

16971694
/* CNL/ICL Port COMP_DW registers */
1695+
#define _ICL_PORT_COMP 0x100
1696+
#define _ICL_PORT_COMP_DW(dw, port) (_ICL_COMBOPHY(port) + \
1697+
_ICL_PORT_COMP + 4 * (dw))
1698+
16981699
#define CNL_PORT_COMP_DW0 _MMIO(0x162100)
1699-
#define _ICL_PORT_COMP_DW0_A 0x162100
1700-
#define _ICL_PORT_COMP_DW0_B 0x6C100
1701-
#define ICL_PORT_COMP_DW0(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW0_A, \
1702-
_ICL_PORT_COMP_DW0_B)
1700+
#define ICL_PORT_COMP_DW0(port) _MMIO(_ICL_PORT_COMP_DW(0, port))
17031701
#define COMP_INIT (1 << 31)
17041702

17051703
#define CNL_PORT_COMP_DW1 _MMIO(0x162104)
1706-
#define _ICL_PORT_COMP_DW1_A 0x162104
1707-
#define _ICL_PORT_COMP_DW1_B 0x6C104
1708-
#define ICL_PORT_COMP_DW1(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW1_A, \
1709-
_ICL_PORT_COMP_DW1_B)
1704+
#define ICL_PORT_COMP_DW1(port) _MMIO(_ICL_PORT_COMP_DW(1, port))
1705+
17101706
#define CNL_PORT_COMP_DW3 _MMIO(0x16210c)
1711-
#define _ICL_PORT_COMP_DW3_A 0x16210C
1712-
#define _ICL_PORT_COMP_DW3_B 0x6C10C
1713-
#define ICL_PORT_COMP_DW3(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW3_A, \
1714-
_ICL_PORT_COMP_DW3_B)
1707+
#define ICL_PORT_COMP_DW3(port) _MMIO(_ICL_PORT_COMP_DW(3, port))
17151708
#define PROCESS_INFO_DOT_0 (0 << 26)
17161709
#define PROCESS_INFO_DOT_1 (1 << 26)
17171710
#define PROCESS_INFO_DOT_4 (2 << 26)
@@ -1724,17 +1717,10 @@ enum i915_power_well_id {
17241717
#define VOLTAGE_INFO_SHIFT 24
17251718

17261719
#define CNL_PORT_COMP_DW9 _MMIO(0x162124)
1727-
#define _ICL_PORT_COMP_DW9_A 0x162124
1728-
#define _ICL_PORT_COMP_DW9_B 0x6C124
1729-
#define ICL_PORT_COMP_DW9(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW9_A, \
1730-
_ICL_PORT_COMP_DW9_B)
1720+
#define ICL_PORT_COMP_DW9(port) _MMIO(_ICL_PORT_COMP_DW(9, port))
17311721

17321722
#define CNL_PORT_COMP_DW10 _MMIO(0x162128)
1733-
#define _ICL_PORT_COMP_DW10_A 0x162128
1734-
#define _ICL_PORT_COMP_DW10_B 0x6C128
1735-
#define ICL_PORT_COMP_DW10(port) _MMIO_PORT(port, \
1736-
_ICL_PORT_COMP_DW10_A, \
1737-
_ICL_PORT_COMP_DW10_B)
1723+
#define ICL_PORT_COMP_DW10(port) _MMIO(_ICL_PORT_COMP_DW(10, port))
17381724

17391725
/* CNL/ICL Port PCS registers */
17401726
#define _CNL_PORT_PCS_DW1_GRP_AE 0x162304
@@ -1754,7 +1740,6 @@ enum i915_power_well_id {
17541740
_CNL_PORT_PCS_DW1_GRP_D, \
17551741
_CNL_PORT_PCS_DW1_GRP_AE, \
17561742
_CNL_PORT_PCS_DW1_GRP_F))
1757-
17581743
#define CNL_PORT_PCS_DW1_LN0(port) _MMIO(_PICK(port, \
17591744
_CNL_PORT_PCS_DW1_LN0_AE, \
17601745
_CNL_PORT_PCS_DW1_LN0_B, \
@@ -1763,21 +1748,18 @@ enum i915_power_well_id {
17631748
_CNL_PORT_PCS_DW1_LN0_AE, \
17641749
_CNL_PORT_PCS_DW1_LN0_F))
17651750

1766-
#define _ICL_PORT_PCS_DW1_GRP_A 0x162604
1767-
#define _ICL_PORT_PCS_DW1_GRP_B 0x6C604
1768-
#define _ICL_PORT_PCS_DW1_LN0_A 0x162804
1769-
#define _ICL_PORT_PCS_DW1_LN0_B 0x6C804
1770-
#define _ICL_PORT_PCS_DW1_AUX_A 0x162304
1771-
#define _ICL_PORT_PCS_DW1_AUX_B 0x6c304
1772-
#define ICL_PORT_PCS_DW1_GRP(port) _MMIO_PORT(port,\
1773-
_ICL_PORT_PCS_DW1_GRP_A, \
1774-
_ICL_PORT_PCS_DW1_GRP_B)
1775-
#define ICL_PORT_PCS_DW1_LN0(port) _MMIO_PORT(port, \
1776-
_ICL_PORT_PCS_DW1_LN0_A, \
1777-
_ICL_PORT_PCS_DW1_LN0_B)
1778-
#define ICL_PORT_PCS_DW1_AUX(port) _MMIO_PORT(port, \
1779-
_ICL_PORT_PCS_DW1_AUX_A, \
1780-
_ICL_PORT_PCS_DW1_AUX_B)
1751+
#define _ICL_PORT_PCS_AUX 0x300
1752+
#define _ICL_PORT_PCS_GRP 0x600
1753+
#define _ICL_PORT_PCS_LN(ln) (0x800 + (ln) * 0x100)
1754+
#define _ICL_PORT_PCS_DW_AUX(dw, port) (_ICL_COMBOPHY(port) + \
1755+
_ICL_PORT_PCS_AUX + 4 * (dw))
1756+
#define _ICL_PORT_PCS_DW_GRP(dw, port) (_ICL_COMBOPHY(port) + \
1757+
_ICL_PORT_PCS_GRP + 4 * (dw))
1758+
#define _ICL_PORT_PCS_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \
1759+
_ICL_PORT_PCS_LN(ln) + 4 * (dw))
1760+
#define ICL_PORT_PCS_DW1_AUX(port) _MMIO(_ICL_PORT_PCS_DW_AUX(1, port))
1761+
#define ICL_PORT_PCS_DW1_GRP(port) _MMIO(_ICL_PORT_PCS_DW_GRP(1, port))
1762+
#define ICL_PORT_PCS_DW1_LN0(port) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, port))
17811763
#define COMMON_KEEPER_EN (1 << 26)
17821764

17831765
/* CNL/ICL Port TX registers */
@@ -1808,23 +1790,22 @@ enum i915_power_well_id {
18081790
_CNL_PORT_TX_F_LN0_OFFSET) + \
18091791
4 * (dw))
18101792

1811-
#define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 2))
1812-
#define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 2))
1813-
#define _ICL_PORT_TX_DW2_GRP_A 0x162688
1814-
#define _ICL_PORT_TX_DW2_GRP_B 0x6C688
1815-
#define _ICL_PORT_TX_DW2_LN0_A 0x162888
1816-
#define _ICL_PORT_TX_DW2_LN0_B 0x6C888
1817-
#define _ICL_PORT_TX_DW2_AUX_A 0x162388
1818-
#define _ICL_PORT_TX_DW2_AUX_B 0x6c388
1819-
#define ICL_PORT_TX_DW2_GRP(port) _MMIO_PORT(port, \
1820-
_ICL_PORT_TX_DW2_GRP_A, \
1821-
_ICL_PORT_TX_DW2_GRP_B)
1822-
#define ICL_PORT_TX_DW2_LN0(port) _MMIO_PORT(port, \
1823-
_ICL_PORT_TX_DW2_LN0_A, \
1824-
_ICL_PORT_TX_DW2_LN0_B)
1825-
#define ICL_PORT_TX_DW2_AUX(port) _MMIO_PORT(port, \
1826-
_ICL_PORT_TX_DW2_AUX_A, \
1827-
_ICL_PORT_TX_DW2_AUX_B)
1793+
#define _ICL_PORT_TX_AUX 0x380
1794+
#define _ICL_PORT_TX_GRP 0x680
1795+
#define _ICL_PORT_TX_LN(ln) (0x880 + (ln) * 0x100)
1796+
1797+
#define _ICL_PORT_TX_DW_AUX(dw, port) (_ICL_COMBOPHY(port) + \
1798+
_ICL_PORT_TX_AUX + 4 * (dw))
1799+
#define _ICL_PORT_TX_DW_GRP(dw, port) (_ICL_COMBOPHY(port) + \
1800+
_ICL_PORT_TX_GRP + 4 * (dw))
1801+
#define _ICL_PORT_TX_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \
1802+
_ICL_PORT_TX_LN(ln) + 4 * (dw))
1803+
1804+
#define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(2, port))
1805+
#define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(2, port))
1806+
#define ICL_PORT_TX_DW2_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(2, port))
1807+
#define ICL_PORT_TX_DW2_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(2, port))
1808+
#define ICL_PORT_TX_DW2_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(2, 0, port))
18281809
#define SWING_SEL_UPPER(x) (((x) >> 3) << 15)
18291810
#define SWING_SEL_UPPER_MASK (1 << 15)
18301811
#define SWING_SEL_LOWER(x) (((x) & 0x7) << 11)
@@ -1841,24 +1822,10 @@ enum i915_power_well_id {
18411822
#define CNL_PORT_TX_DW4_LN(port, ln) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4) + \
18421823
((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
18431824
_CNL_PORT_TX_DW4_LN0_AE)))
1844-
#define _ICL_PORT_TX_DW4_GRP_A 0x162690
1845-
#define _ICL_PORT_TX_DW4_GRP_B 0x6C690
1846-
#define _ICL_PORT_TX_DW4_LN0_A 0x162890
1847-
#define _ICL_PORT_TX_DW4_LN1_A 0x162990
1848-
#define _ICL_PORT_TX_DW4_LN0_B 0x6C890
1849-
#define _ICL_PORT_TX_DW4_AUX_A 0x162390
1850-
#define _ICL_PORT_TX_DW4_AUX_B 0x6c390
1851-
#define ICL_PORT_TX_DW4_GRP(port) _MMIO_PORT(port, \
1852-
_ICL_PORT_TX_DW4_GRP_A, \
1853-
_ICL_PORT_TX_DW4_GRP_B)
1854-
#define ICL_PORT_TX_DW4_LN(port, ln) _MMIO(_PORT(port, \
1855-
_ICL_PORT_TX_DW4_LN0_A, \
1856-
_ICL_PORT_TX_DW4_LN0_B) + \
1857-
((ln) * (_ICL_PORT_TX_DW4_LN1_A - \
1858-
_ICL_PORT_TX_DW4_LN0_A)))
1859-
#define ICL_PORT_TX_DW4_AUX(port) _MMIO_PORT(port, \
1860-
_ICL_PORT_TX_DW4_AUX_A, \
1861-
_ICL_PORT_TX_DW4_AUX_B)
1825+
#define ICL_PORT_TX_DW4_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(4, port))
1826+
#define ICL_PORT_TX_DW4_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(4, port))
1827+
#define ICL_PORT_TX_DW4_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(4, 0, port))
1828+
#define ICL_PORT_TX_DW4_LN(port, ln) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, port))
18621829
#define LOADGEN_SELECT (1 << 31)
18631830
#define POST_CURSOR_1(x) ((x) << 12)
18641831
#define POST_CURSOR_1_MASK (0x3F << 12)
@@ -1867,23 +1834,11 @@ enum i915_power_well_id {
18671834
#define CURSOR_COEFF(x) ((x) << 0)
18681835
#define CURSOR_COEFF_MASK (0x3F << 0)
18691836

1870-
#define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 5))
1871-
#define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 5))
1872-
#define _ICL_PORT_TX_DW5_GRP_A 0x162694
1873-
#define _ICL_PORT_TX_DW5_GRP_B 0x6C694
1874-
#define _ICL_PORT_TX_DW5_LN0_A 0x162894
1875-
#define _ICL_PORT_TX_DW5_LN0_B 0x6C894
1876-
#define _ICL_PORT_TX_DW5_AUX_A 0x162394
1877-
#define _ICL_PORT_TX_DW5_AUX_B 0x6c394
1878-
#define ICL_PORT_TX_DW5_GRP(port) _MMIO_PORT(port, \
1879-
_ICL_PORT_TX_DW5_GRP_A, \
1880-
_ICL_PORT_TX_DW5_GRP_B)
1881-
#define ICL_PORT_TX_DW5_LN0(port) _MMIO_PORT(port, \
1882-
_ICL_PORT_TX_DW5_LN0_A, \
1883-
_ICL_PORT_TX_DW5_LN0_B)
1884-
#define ICL_PORT_TX_DW5_AUX(port) _MMIO_PORT(port, \
1885-
_ICL_PORT_TX_DW5_AUX_A, \
1886-
_ICL_PORT_TX_DW5_AUX_B)
1837+
#define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(5, port))
1838+
#define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(5, port))
1839+
#define ICL_PORT_TX_DW5_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(5, port))
1840+
#define ICL_PORT_TX_DW5_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(5, port))
1841+
#define ICL_PORT_TX_DW5_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(5, 0, port))
18871842
#define TX_TRAINING_EN (1 << 31)
18881843
#define TAP2_DISABLE (1 << 30)
18891844
#define TAP3_DISABLE (1 << 29)

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