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mrutland-armwildea01
mrutland-arm
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wildea01
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arm64: cpufeature: remove explicit RAZ fields
We currently have some RAZ fields described explicitly in our arm64_ftr_bits arrays. These are inconsistently commented, grouped, and/or applied, and maintaining these is error-prone. Luckily, we don't need these at all. We'll never need to inspect RAZ fields to determine feature support, and init_cpu_ftr_reg() will ensure that any bits without a corresponding arm64_ftr_bits entry are treated as RES0 with strict matching requirements. In check_update_ftr_reg() we'll then compare these bits from the relevant cpuinfo_arm64 structures, and need not store them in a arm64_ftr_reg. This patch removes the unnecessary arm64_ftr_bits entries for RES0 bits. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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‎arch/arm64/kernel/cpufeature.c

Lines changed: 0 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -81,21 +81,16 @@ cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
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8282

8383
static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
84-
ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
86-
ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
92-
ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
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ARM64_FTR_END,
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};
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static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
97-
ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0),
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S_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
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S_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
@@ -108,7 +103,6 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
108103
};
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static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
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S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
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S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
@@ -126,7 +120,6 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
126120
};
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static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
@@ -147,7 +140,6 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
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static const struct arm64_ftr_bits ftr_ctr[] = {
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RAO */
150-
ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 3, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0), /* CWG */
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ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), /* ERG */
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ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */
@@ -157,7 +149,6 @@ static const struct arm64_ftr_bits ftr_ctr[] = {
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* If we have differing I-cache policies, report it as the weakest - AIVIVT.
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*/
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ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_AIVIVT), /* L1Ip */
160-
ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 10, 0), /* RAZ */
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ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* IminLine */
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ARM64_FTR_END,
163154
};
@@ -196,14 +187,12 @@ static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
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};
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static const struct arm64_ftr_bits ftr_mvfr2[] = {
199-
ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0), /* RAZ */
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* FPMisc */
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* SIMDMisc */
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ARM64_FTR_END,
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};
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205195
static const struct arm64_ftr_bits ftr_dczid[] = {
206-
ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 5, 27, 0), /* RAZ */
207196
ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */
208197
ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */
209198
ARM64_FTR_END,
@@ -212,7 +201,6 @@ static const struct arm64_ftr_bits ftr_dczid[] = {
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213202
static const struct arm64_ftr_bits ftr_id_isar5[] = {
214203
ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_RDM_SHIFT, 4, 0),
215-
ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 20, 4, 0), /* RAZ */
216204
ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_CRC32_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA2_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA1_SHIFT, 4, 0),
@@ -222,14 +210,11 @@ static const struct arm64_ftr_bits ftr_id_isar5[] = {
222210
};
223211

224212
static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
225-
ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0), /* RAZ */
226213
ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* ac2 */
227-
ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
228214
ARM64_FTR_END,
229215
};
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231217
static const struct arm64_ftr_bits ftr_id_pfr0[] = {
232-
ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 16, 0), /* RAZ */
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0), /* State3 */
234219
ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0), /* State2 */
235220
ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* State1 */

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