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torvaldstorvalds
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Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 TLB detection update from Ingo Molnar: "A single change that extends our TLB cache size detection+reporting code" * 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86, cpu: Detect more TLB configuration
2 parents 2a0fede + dd36039 commit 5d4863e

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3 files changed

+31
-3
lines changed

3 files changed

+31
-3
lines changed

‎arch/x86/include/asm/processor.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -71,6 +71,7 @@ extern u16 __read_mostly tlb_lli_4m[NR_INFO];
7171
extern u16 __read_mostly tlb_lld_4k[NR_INFO];
7272
extern u16 __read_mostly tlb_lld_2m[NR_INFO];
7373
extern u16 __read_mostly tlb_lld_4m[NR_INFO];
74+
extern u16 __read_mostly tlb_lld_1g[NR_INFO];
7475
extern s8 __read_mostly tlb_flushall_shift;
7576

7677
/*

‎arch/x86/kernel/cpu/common.c

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -472,6 +472,7 @@ u16 __read_mostly tlb_lli_4m[NR_INFO];
472472
u16 __read_mostly tlb_lld_4k[NR_INFO];
473473
u16 __read_mostly tlb_lld_2m[NR_INFO];
474474
u16 __read_mostly tlb_lld_4m[NR_INFO];
475+
u16 __read_mostly tlb_lld_1g[NR_INFO];
475476

476477
/*
477478
* tlb_flushall_shift shows the balance point in replacing cr3 write
@@ -486,13 +487,13 @@ void cpu_detect_tlb(struct cpuinfo_x86 *c)
486487
if (this_cpu->c_detect_tlb)
487488
this_cpu->c_detect_tlb(c);
488489

489-
printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n" \
490-
"Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d\n" \
490+
printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n"
491+
"Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n"
491492
"tlb_flushall_shift: %d\n",
492493
tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
493494
tlb_lli_4m[ENTRIES], tlb_lld_4k[ENTRIES],
494495
tlb_lld_2m[ENTRIES], tlb_lld_4m[ENTRIES],
495-
tlb_flushall_shift);
496+
tlb_lld_1g[ENTRIES], tlb_flushall_shift);
496497
}
497498

498499
void detect_ht(struct cpuinfo_x86 *c)

‎arch/x86/kernel/cpu/intel.c

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -505,6 +505,7 @@ static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
505505
#define TLB_DATA0_2M_4M 0x23
506506

507507
#define STLB_4K 0x41
508+
#define STLB_4K_2M 0x42
508509

509510
static const struct _tlb_table intel_tlb_table[] = {
510511
{ 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
@@ -525,13 +526,20 @@ static const struct _tlb_table intel_tlb_table[] = {
525526
{ 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
526527
{ 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
527528
{ 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
529+
{ 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" },
530+
{ 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
531+
{ 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
528532
{ 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
529533
{ 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
530534
{ 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
531535
{ 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
532536
{ 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
537+
{ 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set ssociative" },
538+
{ 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set ssociative" },
533539
{ 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
534540
{ 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
541+
{ 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
542+
{ 0xc2, TLB_DATA_2M_4M, 16, " DTLB 2 MByte/4MByte pages, 4-way associative" },
535543
{ 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
536544
{ 0x00, 0, 0 }
537545
};
@@ -557,6 +565,20 @@ static void intel_tlb_lookup(const unsigned char desc)
557565
if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
558566
tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
559567
break;
568+
case STLB_4K_2M:
569+
if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
570+
tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
571+
if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
572+
tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
573+
if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
574+
tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
575+
if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
576+
tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
577+
if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
578+
tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
579+
if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
580+
tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
581+
break;
560582
case TLB_INST_ALL:
561583
if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
562584
tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
@@ -602,6 +624,10 @@ static void intel_tlb_lookup(const unsigned char desc)
602624
if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
603625
tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
604626
break;
627+
case TLB_DATA_1G:
628+
if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)
629+
tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;
630+
break;
605631
}
606632
}
607633

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