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zlimwildea01
zlim
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arm64: introduce aarch64_insn_gen_data2()
Introduce function to generate data-processing (2 source) instructions. Signed-off-by: Zi Shen Lim <zlim.lnx@gmail.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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‎arch/arm64/include/asm/insn.h

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -191,6 +191,15 @@ enum aarch64_insn_data1_type {
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AARCH64_INSN_DATA1_REVERSE_64,
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};
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enum aarch64_insn_data2_type {
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AARCH64_INSN_DATA2_UDIV,
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AARCH64_INSN_DATA2_SDIV,
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AARCH64_INSN_DATA2_LSLV,
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AARCH64_INSN_DATA2_LSRV,
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AARCH64_INSN_DATA2_ASRV,
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AARCH64_INSN_DATA2_RORV,
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};
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#define __AARCH64_INSN_FUNCS(abbr, mask, val) \
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static __always_inline bool aarch64_insn_is_##abbr(u32 code) \
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{ return (code & (mask)) == (val); } \
@@ -217,6 +226,12 @@ __AARCH64_INSN_FUNCS(add, 0x7F200000, 0x0B000000)
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__AARCH64_INSN_FUNCS(adds, 0x7F200000, 0x2B000000)
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__AARCH64_INSN_FUNCS(sub, 0x7F200000, 0x4B000000)
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__AARCH64_INSN_FUNCS(subs, 0x7F200000, 0x6B000000)
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__AARCH64_INSN_FUNCS(udiv, 0x7FE0FC00, 0x1AC00800)
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__AARCH64_INSN_FUNCS(sdiv, 0x7FE0FC00, 0x1AC00C00)
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__AARCH64_INSN_FUNCS(lslv, 0x7FE0FC00, 0x1AC02000)
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__AARCH64_INSN_FUNCS(lsrv, 0x7FE0FC00, 0x1AC02400)
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__AARCH64_INSN_FUNCS(asrv, 0x7FE0FC00, 0x1AC02800)
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__AARCH64_INSN_FUNCS(rorv, 0x7FE0FC00, 0x1AC02C00)
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__AARCH64_INSN_FUNCS(rev16, 0x7FFFFC00, 0x5AC00400)
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__AARCH64_INSN_FUNCS(rev32, 0x7FFFFC00, 0x5AC00800)
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__AARCH64_INSN_FUNCS(rev64, 0x7FFFFC00, 0x5AC00C00)
@@ -289,6 +304,11 @@ u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst,
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enum aarch64_insn_register src,
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enum aarch64_insn_variant variant,
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enum aarch64_insn_data1_type type);
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u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst,
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enum aarch64_insn_register src,
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enum aarch64_insn_register reg,
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enum aarch64_insn_variant variant,
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enum aarch64_insn_data2_type type);
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bool aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn);
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‎arch/arm64/kernel/insn.c

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -784,3 +784,51 @@ u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst,
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return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
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}
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u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst,
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enum aarch64_insn_register src,
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enum aarch64_insn_register reg,
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enum aarch64_insn_variant variant,
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enum aarch64_insn_data2_type type)
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{
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u32 insn;
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switch (type) {
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case AARCH64_INSN_DATA2_UDIV:
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insn = aarch64_insn_get_udiv_value();
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break;
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case AARCH64_INSN_DATA2_SDIV:
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insn = aarch64_insn_get_sdiv_value();
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break;
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case AARCH64_INSN_DATA2_LSLV:
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insn = aarch64_insn_get_lslv_value();
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break;
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case AARCH64_INSN_DATA2_LSRV:
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insn = aarch64_insn_get_lsrv_value();
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break;
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case AARCH64_INSN_DATA2_ASRV:
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insn = aarch64_insn_get_asrv_value();
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break;
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case AARCH64_INSN_DATA2_RORV:
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insn = aarch64_insn_get_rorv_value();
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break;
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default:
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BUG_ON(1);
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}
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switch (variant) {
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case AARCH64_INSN_VARIANT_32BIT:
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break;
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case AARCH64_INSN_VARIANT_64BIT:
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insn |= AARCH64_INSN_SF_BIT;
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break;
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default:
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BUG_ON(1);
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}
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insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
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insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
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return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg);
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}

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