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chelsiocudbgdavem330
chelsiocudbg
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cxgb4: collect hardware misc dumps
Collect path mtu, PM stats, TP clock info, congestion control, and VPD data dumps. Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
1 parent 08c4901 commit 6f92a65

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5 files changed

+211
-0
lines changed

5 files changed

+211
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lines changed

‎drivers/net/ethernet/chelsio/cxgb4/cudbg_entity.h

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -49,6 +49,13 @@ struct cudbg_rss_vf_conf {
4949
u32 rss_vf_vfh;
5050
};
5151

52+
struct cudbg_pm_stats {
53+
u32 tx_cnt[T6_PM_NSTATS];
54+
u32 rx_cnt[T6_PM_NSTATS];
55+
u64 tx_cyc[T6_PM_NSTATS];
56+
u64 rx_cyc[T6_PM_NSTATS];
57+
};
58+
5259
struct cudbg_hw_sched {
5360
u32 kbps[NTX_SCHED];
5461
u32 ipg[NTX_SCHED];
@@ -85,6 +92,22 @@ struct cudbg_cim_pif_la {
8592
u8 data[0];
8693
};
8794

95+
struct cudbg_clk_info {
96+
u64 retransmit_min;
97+
u64 retransmit_max;
98+
u64 persist_timer_min;
99+
u64 persist_timer_max;
100+
u64 keepalive_idle_timer;
101+
u64 keepalive_interval;
102+
u64 initial_srtt;
103+
u64 finwait2_timer;
104+
u32 dack_timer;
105+
u32 res;
106+
u32 cclk_ps;
107+
u32 tre;
108+
u32 dack_re;
109+
};
110+
88111
struct cudbg_tid_info_region {
89112
u32 ntids;
90113
u32 nstids;
@@ -143,6 +166,19 @@ struct cudbg_mps_tcam {
143166
u8 reserved[2];
144167
};
145168

169+
struct cudbg_vpd_data {
170+
u8 sn[SERNUM_LEN + 1];
171+
u8 bn[PN_LEN + 1];
172+
u8 na[MACADDR_LEN + 1];
173+
u8 mn[ID_LEN + 1];
174+
u16 fw_major;
175+
u16 fw_minor;
176+
u16 fw_micro;
177+
u16 fw_build;
178+
u32 scfg_vers;
179+
u32 vpd_vers;
180+
};
181+
146182
#define CUDBG_NUM_ULPTX 11
147183
#define CUDBG_NUM_ULPTX_READ 512
148184

‎drivers/net/ethernet/chelsio/cxgb4/cudbg_if.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -49,18 +49,23 @@ enum cudbg_dbg_entity_type {
4949
CUDBG_EDC1 = 19,
5050
CUDBG_RSS = 22,
5151
CUDBG_RSS_VF_CONF = 25,
52+
CUDBG_PATH_MTU = 27,
53+
CUDBG_PM_STATS = 30,
5254
CUDBG_HW_SCHED = 31,
5355
CUDBG_TP_INDIRECT = 36,
5456
CUDBG_SGE_INDIRECT = 37,
5557
CUDBG_ULPRX_LA = 41,
5658
CUDBG_TP_LA = 43,
5759
CUDBG_CIM_PIF_LA = 45,
60+
CUDBG_CLK = 46,
5861
CUDBG_CIM_OBQ_RXQ0 = 47,
5962
CUDBG_CIM_OBQ_RXQ1 = 48,
6063
CUDBG_PCIE_INDIRECT = 50,
6164
CUDBG_PM_INDIRECT = 51,
6265
CUDBG_TID_INFO = 54,
6366
CUDBG_MPS_TCAM = 57,
67+
CUDBG_VPD_DATA = 58,
68+
CUDBG_CCTRL = 60,
6469
CUDBG_MA_INDIRECT = 61,
6570
CUDBG_ULPTX_LA = 62,
6671
CUDBG_UP_CIM_INDIRECT = 64,

‎drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c

Lines changed: 135 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -574,6 +574,44 @@ int cudbg_collect_rss_vf_config(struct cudbg_init *pdbg_init,
574574
return rc;
575575
}
576576

577+
int cudbg_collect_path_mtu(struct cudbg_init *pdbg_init,
578+
struct cudbg_buffer *dbg_buff,
579+
struct cudbg_error *cudbg_err)
580+
{
581+
struct adapter *padap = pdbg_init->adap;
582+
struct cudbg_buffer temp_buff = { 0 };
583+
int rc;
584+
585+
rc = cudbg_get_buff(dbg_buff, NMTUS * sizeof(u16), &temp_buff);
586+
if (rc)
587+
return rc;
588+
589+
t4_read_mtu_tbl(padap, (u16 *)temp_buff.data, NULL);
590+
cudbg_write_and_release_buff(&temp_buff, dbg_buff);
591+
return rc;
592+
}
593+
594+
int cudbg_collect_pm_stats(struct cudbg_init *pdbg_init,
595+
struct cudbg_buffer *dbg_buff,
596+
struct cudbg_error *cudbg_err)
597+
{
598+
struct adapter *padap = pdbg_init->adap;
599+
struct cudbg_buffer temp_buff = { 0 };
600+
struct cudbg_pm_stats *pm_stats_buff;
601+
int rc;
602+
603+
rc = cudbg_get_buff(dbg_buff, sizeof(struct cudbg_pm_stats),
604+
&temp_buff);
605+
if (rc)
606+
return rc;
607+
608+
pm_stats_buff = (struct cudbg_pm_stats *)temp_buff.data;
609+
t4_pmtx_get_stats(padap, pm_stats_buff->tx_cnt, pm_stats_buff->tx_cyc);
610+
t4_pmrx_get_stats(padap, pm_stats_buff->rx_cnt, pm_stats_buff->rx_cyc);
611+
cudbg_write_and_release_buff(&temp_buff, dbg_buff);
612+
return rc;
613+
}
614+
577615
int cudbg_collect_hw_sched(struct cudbg_init *pdbg_init,
578616
struct cudbg_buffer *dbg_buff,
579617
struct cudbg_error *cudbg_err)
@@ -813,6 +851,55 @@ int cudbg_collect_cim_pif_la(struct cudbg_init *pdbg_init,
813851
return rc;
814852
}
815853

854+
int cudbg_collect_clk_info(struct cudbg_init *pdbg_init,
855+
struct cudbg_buffer *dbg_buff,
856+
struct cudbg_error *cudbg_err)
857+
{
858+
struct adapter *padap = pdbg_init->adap;
859+
struct cudbg_buffer temp_buff = { 0 };
860+
struct cudbg_clk_info *clk_info_buff;
861+
u64 tp_tick_us;
862+
int rc;
863+
864+
if (!padap->params.vpd.cclk)
865+
return CUDBG_STATUS_CCLK_NOT_DEFINED;
866+
867+
rc = cudbg_get_buff(dbg_buff, sizeof(struct cudbg_clk_info),
868+
&temp_buff);
869+
if (rc)
870+
return rc;
871+
872+
clk_info_buff = (struct cudbg_clk_info *)temp_buff.data;
873+
clk_info_buff->cclk_ps = 1000000000 / padap->params.vpd.cclk; /* psec */
874+
clk_info_buff->res = t4_read_reg(padap, TP_TIMER_RESOLUTION_A);
875+
clk_info_buff->tre = TIMERRESOLUTION_G(clk_info_buff->res);
876+
clk_info_buff->dack_re = DELAYEDACKRESOLUTION_G(clk_info_buff->res);
877+
tp_tick_us = (clk_info_buff->cclk_ps << clk_info_buff->tre) / 1000000;
878+
879+
clk_info_buff->dack_timer =
880+
(clk_info_buff->cclk_ps << clk_info_buff->dack_re) / 1000000 *
881+
t4_read_reg(padap, TP_DACK_TIMER_A);
882+
clk_info_buff->retransmit_min =
883+
tp_tick_us * t4_read_reg(padap, TP_RXT_MIN_A);
884+
clk_info_buff->retransmit_max =
885+
tp_tick_us * t4_read_reg(padap, TP_RXT_MAX_A);
886+
clk_info_buff->persist_timer_min =
887+
tp_tick_us * t4_read_reg(padap, TP_PERS_MIN_A);
888+
clk_info_buff->persist_timer_max =
889+
tp_tick_us * t4_read_reg(padap, TP_PERS_MAX_A);
890+
clk_info_buff->keepalive_idle_timer =
891+
tp_tick_us * t4_read_reg(padap, TP_KEEP_IDLE_A);
892+
clk_info_buff->keepalive_interval =
893+
tp_tick_us * t4_read_reg(padap, TP_KEEP_INTVL_A);
894+
clk_info_buff->initial_srtt =
895+
tp_tick_us * INITSRTT_G(t4_read_reg(padap, TP_INIT_SRTT_A));
896+
clk_info_buff->finwait2_timer =
897+
tp_tick_us * t4_read_reg(padap, TP_FINWAIT2_TIMER_A);
898+
899+
cudbg_write_and_release_buff(&temp_buff, dbg_buff);
900+
return rc;
901+
}
902+
816903
int cudbg_collect_pcie_indirect(struct cudbg_init *pdbg_init,
817904
struct cudbg_buffer *dbg_buff,
818905
struct cudbg_error *cudbg_err)
@@ -1196,6 +1283,54 @@ int cudbg_collect_mps_tcam(struct cudbg_init *pdbg_init,
11961283
return rc;
11971284
}
11981285

1286+
int cudbg_collect_vpd_data(struct cudbg_init *pdbg_init,
1287+
struct cudbg_buffer *dbg_buff,
1288+
struct cudbg_error *cudbg_err)
1289+
{
1290+
struct adapter *padap = pdbg_init->adap;
1291+
struct cudbg_buffer temp_buff = { 0 };
1292+
struct cudbg_vpd_data *vpd_data;
1293+
int rc;
1294+
1295+
rc = cudbg_get_buff(dbg_buff, sizeof(struct cudbg_vpd_data),
1296+
&temp_buff);
1297+
if (rc)
1298+
return rc;
1299+
1300+
vpd_data = (struct cudbg_vpd_data *)temp_buff.data;
1301+
memcpy(vpd_data->sn, padap->params.vpd.sn, SERNUM_LEN + 1);
1302+
memcpy(vpd_data->bn, padap->params.vpd.pn, PN_LEN + 1);
1303+
memcpy(vpd_data->na, padap->params.vpd.na, MACADDR_LEN + 1);
1304+
memcpy(vpd_data->mn, padap->params.vpd.id, ID_LEN + 1);
1305+
vpd_data->scfg_vers = padap->params.scfg_vers;
1306+
vpd_data->vpd_vers = padap->params.vpd_vers;
1307+
vpd_data->fw_major = FW_HDR_FW_VER_MAJOR_G(padap->params.fw_vers);
1308+
vpd_data->fw_minor = FW_HDR_FW_VER_MINOR_G(padap->params.fw_vers);
1309+
vpd_data->fw_micro = FW_HDR_FW_VER_MICRO_G(padap->params.fw_vers);
1310+
vpd_data->fw_build = FW_HDR_FW_VER_BUILD_G(padap->params.fw_vers);
1311+
cudbg_write_and_release_buff(&temp_buff, dbg_buff);
1312+
return rc;
1313+
}
1314+
1315+
int cudbg_collect_cctrl(struct cudbg_init *pdbg_init,
1316+
struct cudbg_buffer *dbg_buff,
1317+
struct cudbg_error *cudbg_err)
1318+
{
1319+
struct adapter *padap = pdbg_init->adap;
1320+
struct cudbg_buffer temp_buff = { 0 };
1321+
u32 size;
1322+
int rc;
1323+
1324+
size = sizeof(u16) * NMTUS * NCCTRL_WIN;
1325+
rc = cudbg_get_buff(dbg_buff, size, &temp_buff);
1326+
if (rc)
1327+
return rc;
1328+
1329+
t4_read_cong_tbl(padap, (void *)temp_buff.data);
1330+
cudbg_write_and_release_buff(&temp_buff, dbg_buff);
1331+
return rc;
1332+
}
1333+
11991334
int cudbg_collect_ma_indirect(struct cudbg_init *pdbg_init,
12001335
struct cudbg_buffer *dbg_buff,
12011336
struct cudbg_error *cudbg_err)

‎drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.h

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -84,6 +84,12 @@ int cudbg_collect_rss_vf_config(struct cudbg_init *pdbg_init,
8484
int cudbg_collect_tp_indirect(struct cudbg_init *pdbg_init,
8585
struct cudbg_buffer *dbg_buff,
8686
struct cudbg_error *cudbg_err);
87+
int cudbg_collect_path_mtu(struct cudbg_init *pdbg_init,
88+
struct cudbg_buffer *dbg_buff,
89+
struct cudbg_error *cudbg_err);
90+
int cudbg_collect_pm_stats(struct cudbg_init *pdbg_init,
91+
struct cudbg_buffer *dbg_buff,
92+
struct cudbg_error *cudbg_err);
8793
int cudbg_collect_hw_sched(struct cudbg_init *pdbg_init,
8894
struct cudbg_buffer *dbg_buff,
8995
struct cudbg_error *cudbg_err);
@@ -99,6 +105,9 @@ int cudbg_collect_tp_la(struct cudbg_init *pdbg_init,
99105
int cudbg_collect_cim_pif_la(struct cudbg_init *pdbg_init,
100106
struct cudbg_buffer *dbg_buff,
101107
struct cudbg_error *cudbg_err);
108+
int cudbg_collect_clk_info(struct cudbg_init *pdbg_init,
109+
struct cudbg_buffer *dbg_buff,
110+
struct cudbg_error *cudbg_err);
102111
int cudbg_collect_obq_sge_rx_q0(struct cudbg_init *pdbg_init,
103112
struct cudbg_buffer *dbg_buff,
104113
struct cudbg_error *cudbg_err);
@@ -117,6 +126,12 @@ int cudbg_collect_tid(struct cudbg_init *pdbg_init,
117126
int cudbg_collect_mps_tcam(struct cudbg_init *pdbg_init,
118127
struct cudbg_buffer *dbg_buff,
119128
struct cudbg_error *cudbg_err);
129+
int cudbg_collect_vpd_data(struct cudbg_init *pdbg_init,
130+
struct cudbg_buffer *dbg_buff,
131+
struct cudbg_error *cudbg_err);
132+
int cudbg_collect_cctrl(struct cudbg_init *pdbg_init,
133+
struct cudbg_buffer *dbg_buff,
134+
struct cudbg_error *cudbg_err);
120135
int cudbg_collect_ma_indirect(struct cudbg_init *pdbg_init,
121136
struct cudbg_buffer *dbg_buff,
122137
struct cudbg_error *cudbg_err);

‎drivers/net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -46,18 +46,23 @@ static const struct cxgb4_collect_entity cxgb4_collect_hw_dump[] = {
4646
{ CUDBG_CIM_OBQ_NCSI, cudbg_collect_cim_obq_ncsi },
4747
{ CUDBG_RSS, cudbg_collect_rss },
4848
{ CUDBG_RSS_VF_CONF, cudbg_collect_rss_vf_config },
49+
{ CUDBG_PATH_MTU, cudbg_collect_path_mtu },
50+
{ CUDBG_PM_STATS, cudbg_collect_pm_stats },
4951
{ CUDBG_HW_SCHED, cudbg_collect_hw_sched },
5052
{ CUDBG_TP_INDIRECT, cudbg_collect_tp_indirect },
5153
{ CUDBG_SGE_INDIRECT, cudbg_collect_sge_indirect },
5254
{ CUDBG_ULPRX_LA, cudbg_collect_ulprx_la },
5355
{ CUDBG_TP_LA, cudbg_collect_tp_la },
5456
{ CUDBG_CIM_PIF_LA, cudbg_collect_cim_pif_la },
57+
{ CUDBG_CLK, cudbg_collect_clk_info },
5558
{ CUDBG_CIM_OBQ_RXQ0, cudbg_collect_obq_sge_rx_q0 },
5659
{ CUDBG_CIM_OBQ_RXQ1, cudbg_collect_obq_sge_rx_q1 },
5760
{ CUDBG_PCIE_INDIRECT, cudbg_collect_pcie_indirect },
5861
{ CUDBG_PM_INDIRECT, cudbg_collect_pm_indirect },
5962
{ CUDBG_TID_INFO, cudbg_collect_tid },
6063
{ CUDBG_MPS_TCAM, cudbg_collect_mps_tcam },
64+
{ CUDBG_VPD_DATA, cudbg_collect_vpd_data },
65+
{ CUDBG_CCTRL, cudbg_collect_cctrl },
6166
{ CUDBG_MA_INDIRECT, cudbg_collect_ma_indirect },
6267
{ CUDBG_ULPTX_LA, cudbg_collect_ulptx_la },
6368
{ CUDBG_UP_CIM_INDIRECT, cudbg_collect_up_cim_indirect },
@@ -157,6 +162,12 @@ static u32 cxgb4_get_entity_length(struct adapter *adap, u32 entity)
157162
len = adap->params.arch.vfcount *
158163
sizeof(struct cudbg_rss_vf_conf);
159164
break;
165+
case CUDBG_PATH_MTU:
166+
len = NMTUS * sizeof(u16);
167+
break;
168+
case CUDBG_PM_STATS:
169+
len = sizeof(struct cudbg_pm_stats);
170+
break;
160171
case CUDBG_HW_SCHED:
161172
len = sizeof(struct cudbg_hw_sched);
162173
break;
@@ -191,6 +202,9 @@ static u32 cxgb4_get_entity_length(struct adapter *adap, u32 entity)
191202
len = sizeof(struct cudbg_cim_pif_la);
192203
len += 2 * CIM_PIFLA_SIZE * 6 * sizeof(u32);
193204
break;
205+
case CUDBG_CLK:
206+
len = sizeof(struct cudbg_clk_info);
207+
break;
194208
case CUDBG_PCIE_INDIRECT:
195209
n = sizeof(t5_pcie_pdbg_array) / (IREG_NUM_ELEM * sizeof(u32));
196210
len = sizeof(struct ireg_buf) * n * 2;
@@ -206,6 +220,12 @@ static u32 cxgb4_get_entity_length(struct adapter *adap, u32 entity)
206220
len = sizeof(struct cudbg_mps_tcam) *
207221
adap->params.arch.mps_tcam_size;
208222
break;
223+
case CUDBG_VPD_DATA:
224+
len = sizeof(struct cudbg_vpd_data);
225+
break;
226+
case CUDBG_CCTRL:
227+
len = sizeof(u16) * NMTUS * NCCTRL_WIN;
228+
break;
209229
case CUDBG_MA_INDIRECT:
210230
if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
211231
n = sizeof(t6_ma_ireg_array) /

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