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Merge branch 'drm-next-4.6' of git://people.freedesktop.org/~agd5f/linux into drm-next
A few other misc cleanups and bug fixes for 4.6. Highlights: - unify endian handling in powerplay - powerplay fixes - fix a regression in 4.5 on boards with no display connectors - fence cleanups and locking fixes - whitespace cleanups and code refactoring in radeon * 'drm-next-4.6' of git://people.freedesktop.org/~agd5f/linux: (35 commits) drm/amdgpu/gfx7: add MTYPE definition drm/amdgpu: removing BO_VAs shouldn't be interruptible drm/amd/powerplay: show uvd/vce power gate enablement for tonga. drm/amd/powerplay: show uvd/vce power gate info for fiji drm/amdgpu: use sched fence if possible drm/amdgpu: move ib.fence to job.fence drm/amdgpu: give a fence param to ib_free drm/amdgpu: include the right version of gmc header files for iceland drm/radeon: fix indentation. drm/amd/powerplay: add uvd/vce dpm enabling flag to fix the performance issue for CZ drm/amdgpu: switch back to 32bit hw fences v2 drm/amdgpu: remove amdgpu_fence_is_signaled drm/amdgpu: drop the extra fence range check v2 drm/amdgpu: signal fences directly in amdgpu_fence_process drm/amdgpu: cleanup amdgpu_fence_wait_empty v2 drm/amdgpu: keep all fences in an RCU protected array v2 drm/amdgpu: add number of hardware submissions to amdgpu_fence_driver_init_ring drm/amdgpu: RCU protected amd_sched_fence_release drm/amdgpu: RCU protected amdgpu_fence_release drm/amdgpu: merge amdgpu_fence_process and _activity ...
2 parents e608787 + b9c743b commit 902d02d

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‎drivers/gpu/drm/amd/amdgpu/amdgpu.h

Lines changed: 13 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -141,7 +141,6 @@ extern unsigned amdgpu_pcie_lane_cap;
141141
#define CIK_CURSOR_HEIGHT 128
142142

143143
struct amdgpu_device;
144-
struct amdgpu_fence;
145144
struct amdgpu_ib;
146145
struct amdgpu_vm;
147146
struct amdgpu_ring;
@@ -348,13 +347,15 @@ struct amdgpu_fence_driver {
348347
uint64_t gpu_addr;
349348
volatile uint32_t *cpu_addr;
350349
/* sync_seq is protected by ring emission lock */
351-
uint64_t sync_seq;
352-
atomic64_t last_seq;
350+
uint32_t sync_seq;
351+
atomic_t last_seq;
353352
bool initialized;
354353
struct amdgpu_irq_src *irq_src;
355354
unsigned irq_type;
356355
struct timer_list fallback_timer;
357-
wait_queue_head_t fence_queue;
356+
unsigned num_fences_mask;
357+
spinlock_t lock;
358+
struct fence **fences;
358359
};
359360

360361
/* some special values for the owner field */
@@ -364,16 +365,6 @@ struct amdgpu_fence_driver {
364365
#define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
365366
#define AMDGPU_FENCE_FLAG_INT (1 << 1)
366367

367-
struct amdgpu_fence {
368-
struct fence base;
369-
370-
/* RB, DMA, etc. */
371-
struct amdgpu_ring *ring;
372-
uint64_t seq;
373-
374-
wait_queue_t fence_wake;
375-
};
376-
377368
struct amdgpu_user_fence {
378369
/* write-back bo */
379370
struct amdgpu_bo *bo;
@@ -385,15 +376,15 @@ int amdgpu_fence_driver_init(struct amdgpu_device *adev);
385376
void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
386377
void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
387378

388-
int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
379+
int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
380+
unsigned num_hw_submission);
389381
int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
390382
struct amdgpu_irq_src *irq_src,
391383
unsigned irq_type);
392384
void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
393385
void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
394386
int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **fence);
395387
void amdgpu_fence_process(struct amdgpu_ring *ring);
396-
int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
397388
int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
398389
unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
399390

@@ -539,11 +530,14 @@ int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
539530
* Assumption is that there won't be hole (all object on same
540531
* alignment).
541532
*/
533+
534+
#define AMDGPU_SA_NUM_FENCE_LISTS 32
535+
542536
struct amdgpu_sa_manager {
543537
wait_queue_head_t wq;
544538
struct amdgpu_bo *bo;
545539
struct list_head *hole;
546-
struct list_head flist[AMDGPU_MAX_RINGS];
540+
struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
547541
struct list_head olist;
548542
unsigned size;
549543
uint64_t gpu_addr;
@@ -727,7 +721,6 @@ struct amdgpu_ib {
727721
uint32_t length_dw;
728722
uint64_t gpu_addr;
729723
uint32_t *ptr;
730-
struct fence *fence;
731724
struct amdgpu_user_fence *user;
732725
struct amdgpu_vm *vm;
733726
unsigned vm_id;
@@ -1143,7 +1136,7 @@ struct amdgpu_gfx {
11431136

11441137
int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
11451138
unsigned size, struct amdgpu_ib *ib);
1146-
void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
1139+
void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, struct fence *f);
11471140
int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
11481141
struct amdgpu_ib *ib, struct fence *last_vm_update,
11491142
struct fence **f);
@@ -1164,7 +1157,6 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
11641157
struct amdgpu_irq_src *irq_src, unsigned irq_type,
11651158
enum amdgpu_ring_type ring_type);
11661159
void amdgpu_ring_fini(struct amdgpu_ring *ring);
1167-
struct amdgpu_ring *amdgpu_ring_from_fence(struct fence *f);
11681160

11691161
/*
11701162
* CS.
@@ -1206,6 +1198,7 @@ struct amdgpu_job {
12061198
struct amdgpu_ring *ring;
12071199
struct amdgpu_sync sync;
12081200
struct amdgpu_ib *ibs;
1201+
struct fence *fence; /* the hw fence */
12091202
uint32_t num_ibs;
12101203
void *owner;
12111204
struct amdgpu_user_fence uf;
@@ -2066,20 +2059,6 @@ void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
20662059
u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
20672060
void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
20682061

2069-
/*
2070-
* Cast helper
2071-
*/
2072-
extern const struct fence_ops amdgpu_fence_ops;
2073-
static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
2074-
{
2075-
struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
2076-
2077-
if (__f->base.ops == &amdgpu_fence_ops)
2078-
return __f;
2079-
2080-
return NULL;
2081-
}
2082-
20832062
/*
20842063
* Registers read & write functions.
20852064
*/

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