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net: am79c961a: avoid %? in inline assembly
The am79c961a.c driver fails to build with clang because of an unusual inline assembly construct: drivers/net/ethernet/amd/am79c961a.c:53:7: error: invalid % escape in inline assembly string "str%?h %1, [%2] @ NET_RAP\n\t" The same change has been done a decade ago in arch/arm as of 6a39dd6 ("[ARM] 3759/2: Remove uses of %?"), but apparently some drivers were missed. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
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‎drivers/net/ethernet/amd/am79c961a.c

Lines changed: 32 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -50,8 +50,8 @@ static const char version[] =
5050
static void write_rreg(u_long base, u_int reg, u_int val)
5151
{
5252
asm volatile(
53-
"str%?h %1, [%2] @ NET_RAP\n\t"
54-
"str%?h %0, [%2, #-4] @ NET_RDP"
53+
"strh %1, [%2] @ NET_RAP\n\t"
54+
"strh %0, [%2, #-4] @ NET_RDP"
5555
:
5656
: "r" (val), "r" (reg), "r" (ISAIO_BASE + 0x0464));
5757
}
@@ -60,8 +60,8 @@ static inline unsigned short read_rreg(u_long base_addr, u_int reg)
6060
{
6161
unsigned short v;
6262
asm volatile(
63-
"str%?h %1, [%2] @ NET_RAP\n\t"
64-
"ldr%?h %0, [%2, #-4] @ NET_RDP"
63+
"strh %1, [%2] @ NET_RAP\n\t"
64+
"ldrh %0, [%2, #-4] @ NET_RDP"
6565
: "=r" (v)
6666
: "r" (reg), "r" (ISAIO_BASE + 0x0464));
6767
return v;
@@ -70,8 +70,8 @@ static inline unsigned short read_rreg(u_long base_addr, u_int reg)
7070
static inline void write_ireg(u_long base, u_int reg, u_int val)
7171
{
7272
asm volatile(
73-
"str%?h %1, [%2] @ NET_RAP\n\t"
74-
"str%?h %0, [%2, #8] @ NET_IDP"
73+
"strh %1, [%2] @ NET_RAP\n\t"
74+
"strh %0, [%2, #8] @ NET_IDP"
7575
:
7676
: "r" (val), "r" (reg), "r" (ISAIO_BASE + 0x0464));
7777
}
@@ -80,8 +80,8 @@ static inline unsigned short read_ireg(u_long base_addr, u_int reg)
8080
{
8181
u_short v;
8282
asm volatile(
83-
"str%?h %1, [%2] @ NAT_RAP\n\t"
84-
"ldr%?h %0, [%2, #8] @ NET_IDP\n\t"
83+
"strh %1, [%2] @ NAT_RAP\n\t"
84+
"ldrh %0, [%2, #8] @ NET_IDP\n\t"
8585
: "=r" (v)
8686
: "r" (reg), "r" (ISAIO_BASE + 0x0464));
8787
return v;
@@ -96,28 +96,28 @@ am_writebuffer(struct net_device *dev, u_int offset, unsigned char *buf, unsigne
9696
offset = ISAMEM_BASE + (offset << 1);
9797
length = (length + 1) & ~1;
9898
if ((int)buf & 2) {
99-
asm volatile("str%?h %2, [%0], #4"
99+
asm volatile("strh %2, [%0], #4"
100100
: "=&r" (offset) : "0" (offset), "r" (buf[0] | (buf[1] << 8)));
101101
buf += 2;
102102
length -= 2;
103103
}
104104
while (length > 8) {
105105
register unsigned int tmp asm("r2"), tmp2 asm("r3");
106106
asm volatile(
107-
"ldm%?ia %0!, {%1, %2}"
107+
"ldmia %0!, {%1, %2}"
108108
: "+r" (buf), "=&r" (tmp), "=&r" (tmp2));
109109
length -= 8;
110110
asm volatile(
111-
"str%?h %1, [%0], #4\n\t"
112-
"mov%? %1, %1, lsr #16\n\t"
113-
"str%?h %1, [%0], #4\n\t"
114-
"str%?h %2, [%0], #4\n\t"
115-
"mov%? %2, %2, lsr #16\n\t"
116-
"str%?h %2, [%0], #4"
111+
"strh %1, [%0], #4\n\t"
112+
"mov %1, %1, lsr #16\n\t"
113+
"strh %1, [%0], #4\n\t"
114+
"strh %2, [%0], #4\n\t"
115+
"mov %2, %2, lsr #16\n\t"
116+
"strh %2, [%0], #4"
117117
: "+r" (offset), "=&r" (tmp), "=&r" (tmp2));
118118
}
119119
while (length > 0) {
120-
asm volatile("str%?h %2, [%0], #4"
120+
asm volatile("strh %2, [%0], #4"
121121
: "=&r" (offset) : "0" (offset), "r" (buf[0] | (buf[1] << 8)));
122122
buf += 2;
123123
length -= 2;
@@ -132,34 +132,34 @@ am_readbuffer(struct net_device *dev, u_int offset, unsigned char *buf, unsigned
132132
if ((int)buf & 2) {
133133
unsigned int tmp;
134134
asm volatile(
135-
"ldr%?h %2, [%0], #4\n\t"
136-
"str%?b %2, [%1], #1\n\t"
137-
"mov%? %2, %2, lsr #8\n\t"
138-
"str%?b %2, [%1], #1"
135+
"ldrh %2, [%0], #4\n\t"
136+
"strb %2, [%1], #1\n\t"
137+
"mov %2, %2, lsr #8\n\t"
138+
"strb %2, [%1], #1"
139139
: "=&r" (offset), "=&r" (buf), "=r" (tmp): "0" (offset), "1" (buf));
140140
length -= 2;
141141
}
142142
while (length > 8) {
143143
register unsigned int tmp asm("r2"), tmp2 asm("r3"), tmp3;
144144
asm volatile(
145-
"ldr%?h %2, [%0], #4\n\t"
146-
"ldr%?h %4, [%0], #4\n\t"
147-
"ldr%?h %3, [%0], #4\n\t"
148-
"orr%? %2, %2, %4, lsl #16\n\t"
149-
"ldr%?h %4, [%0], #4\n\t"
150-
"orr%? %3, %3, %4, lsl #16\n\t"
151-
"stm%?ia %1!, {%2, %3}"
145+
"ldrh %2, [%0], #4\n\t"
146+
"ldrh %4, [%0], #4\n\t"
147+
"ldrh %3, [%0], #4\n\t"
148+
"orr %2, %2, %4, lsl #16\n\t"
149+
"ldrh %4, [%0], #4\n\t"
150+
"orr %3, %3, %4, lsl #16\n\t"
151+
"stmia %1!, {%2, %3}"
152152
: "=&r" (offset), "=&r" (buf), "=r" (tmp), "=r" (tmp2), "=r" (tmp3)
153153
: "0" (offset), "1" (buf));
154154
length -= 8;
155155
}
156156
while (length > 0) {
157157
unsigned int tmp;
158158
asm volatile(
159-
"ldr%?h %2, [%0], #4\n\t"
160-
"str%?b %2, [%1], #1\n\t"
161-
"mov%? %2, %2, lsr #8\n\t"
162-
"str%?b %2, [%1], #1"
159+
"ldrh %2, [%0], #4\n\t"
160+
"strb %2, [%1], #1\n\t"
161+
"mov %2, %2, lsr #8\n\t"
162+
"strb %2, [%1], #1"
163163
: "=&r" (offset), "=&r" (buf), "=r" (tmp) : "0" (offset), "1" (buf));
164164
length -= 2;
165165
}

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