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Achiad Shochatdavem330
Achiad Shochat
authored and
davem330
committed
net/mlx5e: Input IPSEC.SPI into the RX RSS hash function
In addition to the source/destination IP which are already hashed. Only for unicast traffic for now. Signed-off-by: Achiad Shochat <achiad@mellanox.com> Signed-off-by: Amir Vadai <amirv@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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3 files changed

+127
-1
lines changed

3 files changed

+127
-1
lines changed

‎drivers/net/ethernet/mellanox/mlx5/core/en.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -334,6 +334,10 @@ enum mlx5e_traffic_types {
334334
MLX5E_TT_IPV6_TCP,
335335
MLX5E_TT_IPV4_UDP,
336336
MLX5E_TT_IPV6_UDP,
337+
MLX5E_TT_IPV4_IPSEC_AH,
338+
MLX5E_TT_IPV6_IPSEC_AH,
339+
MLX5E_TT_IPV4_IPSEC_ESP,
340+
MLX5E_TT_IPV6_IPSEC_ESP,
337341
MLX5E_TT_IPV4,
338342
MLX5E_TT_IPV6,
339343
MLX5E_TT_ANY,

‎drivers/net/ethernet/mellanox/mlx5/core/en_flow_table.c

Lines changed: 91 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -105,6 +105,22 @@ static void mlx5e_del_eth_addr_from_flow_table(struct mlx5e_priv *priv,
105105
{
106106
void *ft = priv->ft.main;
107107

108+
if (ai->tt_vec & BIT(MLX5E_TT_IPV6_IPSEC_ESP))
109+
mlx5_del_flow_table_entry(ft,
110+
ai->ft_ix[MLX5E_TT_IPV6_IPSEC_ESP]);
111+
112+
if (ai->tt_vec & BIT(MLX5E_TT_IPV4_IPSEC_ESP))
113+
mlx5_del_flow_table_entry(ft,
114+
ai->ft_ix[MLX5E_TT_IPV4_IPSEC_ESP]);
115+
116+
if (ai->tt_vec & BIT(MLX5E_TT_IPV6_IPSEC_AH))
117+
mlx5_del_flow_table_entry(ft,
118+
ai->ft_ix[MLX5E_TT_IPV6_IPSEC_AH]);
119+
120+
if (ai->tt_vec & BIT(MLX5E_TT_IPV4_IPSEC_AH))
121+
mlx5_del_flow_table_entry(ft,
122+
ai->ft_ix[MLX5E_TT_IPV4_IPSEC_AH]);
123+
108124
if (ai->tt_vec & BIT(MLX5E_TT_IPV6_TCP))
109125
mlx5_del_flow_table_entry(ft, ai->ft_ix[MLX5E_TT_IPV6_TCP]);
110126

@@ -160,6 +176,10 @@ static u32 mlx5e_get_tt_vec(struct mlx5e_eth_addr_info *ai, int type)
160176
BIT(MLX5E_TT_IPV6_TCP) |
161177
BIT(MLX5E_TT_IPV4_UDP) |
162178
BIT(MLX5E_TT_IPV6_UDP) |
179+
BIT(MLX5E_TT_IPV4_IPSEC_AH) |
180+
BIT(MLX5E_TT_IPV6_IPSEC_AH) |
181+
BIT(MLX5E_TT_IPV4_IPSEC_ESP) |
182+
BIT(MLX5E_TT_IPV6_IPSEC_ESP) |
163183
BIT(MLX5E_TT_IPV4) |
164184
BIT(MLX5E_TT_IPV6) |
165185
BIT(MLX5E_TT_ANY) |
@@ -205,6 +225,10 @@ static u32 mlx5e_get_tt_vec(struct mlx5e_eth_addr_info *ai, int type)
205225
BIT(MLX5E_TT_IPV6_TCP) |
206226
BIT(MLX5E_TT_IPV4_UDP) |
207227
BIT(MLX5E_TT_IPV6_UDP) |
228+
BIT(MLX5E_TT_IPV4_IPSEC_AH) |
229+
BIT(MLX5E_TT_IPV6_IPSEC_AH) |
230+
BIT(MLX5E_TT_IPV4_IPSEC_ESP) |
231+
BIT(MLX5E_TT_IPV6_IPSEC_ESP) |
208232
BIT(MLX5E_TT_IPV4) |
209233
BIT(MLX5E_TT_IPV6) |
210234
BIT(MLX5E_TT_ANY) |
@@ -377,6 +401,72 @@ static int __mlx5e_add_eth_addr_rule(struct mlx5e_priv *priv,
377401
ai->tt_vec |= BIT(MLX5E_TT_IPV6_TCP);
378402
}
379403

404+
MLX5_SET(fte_match_param, match_value, outer_headers.ip_protocol,
405+
IPPROTO_AH);
406+
407+
ft_ix = &ai->ft_ix[MLX5E_TT_IPV4_IPSEC_AH];
408+
if (tt_vec & BIT(MLX5E_TT_IPV4_IPSEC_AH)) {
409+
MLX5_SET(fte_match_param, match_value, outer_headers.ethertype,
410+
ETH_P_IP);
411+
MLX5_SET(dest_format_struct, dest, destination_id,
412+
tirn[MLX5E_TT_IPV4_IPSEC_AH]);
413+
err = mlx5_add_flow_table_entry(ft, match_criteria_enable,
414+
match_criteria, flow_context,
415+
ft_ix);
416+
if (err)
417+
goto err_del_ai;
418+
419+
ai->tt_vec |= BIT(MLX5E_TT_IPV4_IPSEC_AH);
420+
}
421+
422+
ft_ix = &ai->ft_ix[MLX5E_TT_IPV6_IPSEC_AH];
423+
if (tt_vec & BIT(MLX5E_TT_IPV6_IPSEC_AH)) {
424+
MLX5_SET(fte_match_param, match_value, outer_headers.ethertype,
425+
ETH_P_IPV6);
426+
MLX5_SET(dest_format_struct, dest, destination_id,
427+
tirn[MLX5E_TT_IPV6_IPSEC_AH]);
428+
err = mlx5_add_flow_table_entry(ft, match_criteria_enable,
429+
match_criteria, flow_context,
430+
ft_ix);
431+
if (err)
432+
goto err_del_ai;
433+
434+
ai->tt_vec |= BIT(MLX5E_TT_IPV6_IPSEC_AH);
435+
}
436+
437+
MLX5_SET(fte_match_param, match_value, outer_headers.ip_protocol,
438+
IPPROTO_ESP);
439+
440+
ft_ix = &ai->ft_ix[MLX5E_TT_IPV4_IPSEC_ESP];
441+
if (tt_vec & BIT(MLX5E_TT_IPV4_IPSEC_ESP)) {
442+
MLX5_SET(fte_match_param, match_value, outer_headers.ethertype,
443+
ETH_P_IP);
444+
MLX5_SET(dest_format_struct, dest, destination_id,
445+
tirn[MLX5E_TT_IPV4_IPSEC_ESP]);
446+
err = mlx5_add_flow_table_entry(ft, match_criteria_enable,
447+
match_criteria, flow_context,
448+
ft_ix);
449+
if (err)
450+
goto err_del_ai;
451+
452+
ai->tt_vec |= BIT(MLX5E_TT_IPV4_IPSEC_ESP);
453+
}
454+
455+
ft_ix = &ai->ft_ix[MLX5E_TT_IPV6_IPSEC_ESP];
456+
if (tt_vec & BIT(MLX5E_TT_IPV6_IPSEC_ESP)) {
457+
MLX5_SET(fte_match_param, match_value, outer_headers.ethertype,
458+
ETH_P_IPV6);
459+
MLX5_SET(dest_format_struct, dest, destination_id,
460+
tirn[MLX5E_TT_IPV6_IPSEC_ESP]);
461+
err = mlx5_add_flow_table_entry(ft, match_criteria_enable,
462+
match_criteria, flow_context,
463+
ft_ix);
464+
if (err)
465+
goto err_del_ai;
466+
467+
ai->tt_vec |= BIT(MLX5E_TT_IPV6_IPSEC_ESP);
468+
}
469+
380470
return 0;
381471

382472
err_del_ai:
@@ -731,7 +821,7 @@ static int mlx5e_create_main_flow_table(struct mlx5e_priv *priv)
731821
if (!g)
732822
return -ENOMEM;
733823

734-
g[0].log_sz = 2;
824+
g[0].log_sz = 3;
735825
g[0].match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
736826
MLX5_SET_TO_ONES(fte_match_param, g[0].match_criteria,
737827
outer_headers.ethertype);

‎drivers/net/ethernet/mellanox/mlx5/core/en_main.c

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1260,6 +1260,10 @@ static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
12601260
MLX5_HASH_FIELD_SEL_L4_SPORT |\
12611261
MLX5_HASH_FIELD_SEL_L4_DPORT)
12621262

1263+
#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
1264+
MLX5_HASH_FIELD_SEL_DST_IP |\
1265+
MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1266+
12631267
if (priv->params.lro_en) {
12641268
MLX5_SET(tirc, tirc, lro_enable_mask,
12651269
MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
@@ -1335,6 +1339,34 @@ static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
13351339
MLX5_HASH_IP_L4PORTS);
13361340
break;
13371341

1342+
case MLX5E_TT_IPV4_IPSEC_AH:
1343+
MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1344+
MLX5_L3_PROT_TYPE_IPV4);
1345+
MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1346+
MLX5_HASH_IP_IPSEC_SPI);
1347+
break;
1348+
1349+
case MLX5E_TT_IPV6_IPSEC_AH:
1350+
MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1351+
MLX5_L3_PROT_TYPE_IPV6);
1352+
MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1353+
MLX5_HASH_IP_IPSEC_SPI);
1354+
break;
1355+
1356+
case MLX5E_TT_IPV4_IPSEC_ESP:
1357+
MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1358+
MLX5_L3_PROT_TYPE_IPV4);
1359+
MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1360+
MLX5_HASH_IP_IPSEC_SPI);
1361+
break;
1362+
1363+
case MLX5E_TT_IPV6_IPSEC_ESP:
1364+
MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1365+
MLX5_L3_PROT_TYPE_IPV6);
1366+
MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1367+
MLX5_HASH_IP_IPSEC_SPI);
1368+
break;
1369+
13381370
case MLX5E_TT_IPV4:
13391371
MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
13401372
MLX5_L3_PROT_TYPE_IPV4);

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