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Andi KleenIngo Molnar
Andi Kleen
authored and
Ingo Molnar
committed
perf: Add support for supplementary event registers
Change logs against Andi's original version: - Extends perf_event_attr:config to config{,1,2} (Peter Zijlstra) - Fixed a major event scheduling issue. There cannot be a ref++ on an event that has already done ref++ once and without calling put_constraint() in between. (Stephane Eranian) - Use thread_cpumask for percore allocation. (Lin Ming) - Use MSR names in the extra reg lists. (Lin Ming) - Remove redundant "c = NULL" in intel_percore_constraints - Fix comment of perf_event_attr::config1 Intel Nehalem/Westmere have a special OFFCORE_RESPONSE event that can be used to monitor any offcore accesses from a core. This is a very useful event for various tunings, and it's also needed to implement the generic LLC-* events correctly. Unfortunately this event requires programming a mask in a separate register. And worse this separate register is per core, not per CPU thread. This patch: - Teaches perf_events that OFFCORE_RESPONSE needs extra parameters. The extra parameters are passed by user space in the perf_event_attr::config1 field. - Adds support to the Intel perf_event core to schedule per core resources. This adds fairly generic infrastructure that can be also used for other per core resources. The basic code has is patterned after the similar AMD northbridge constraints code. Thanks to Stephane Eranian who pointed out some problems in the original version and suggested improvements. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Lin Ming <ming.m.lin@intel.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <1299119690-13991-2-git-send-email-ming.m.lin@intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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‎arch/x86/include/asm/msr-index.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,9 @@
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#define MSR_IA32_MCG_STATUS 0x0000017a
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#define MSR_IA32_MCG_CTL 0x0000017b
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#define MSR_OFFCORE_RSP_0 0x000001a6
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#define MSR_OFFCORE_RSP_1 0x000001a7
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#define MSR_IA32_PEBS_ENABLE 0x000003f1
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#define MSR_IA32_DS_AREA 0x00000600
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#define MSR_IA32_PERF_CAPABILITIES 0x00000345

‎arch/x86/kernel/cpu/perf_event.c

Lines changed: 64 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -93,6 +93,8 @@ struct amd_nb {
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struct event_constraint event_constraints[X86_PMC_IDX_MAX];
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};
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struct intel_percore;
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9698
#define MAX_LBR_ENTRIES 16
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struct cpu_hw_events {
@@ -127,6 +129,13 @@ struct cpu_hw_events {
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struct perf_branch_stack lbr_stack;
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struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
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/*
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* Intel percore register state.
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* Coordinate shared resources between HT threads.
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*/
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int percore_used; /* Used by this CPU? */
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struct intel_percore *per_core;
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/*
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* AMD specific bits
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*/
@@ -177,6 +186,28 @@ struct cpu_hw_events {
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#define for_each_event_constraint(e, c) \
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for ((e) = (c); (e)->weight; (e)++)
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/*
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* Extra registers for specific events.
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* Some events need large masks and require external MSRs.
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* Define a mapping to these extra registers.
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*/
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struct extra_reg {
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unsigned int event;
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unsigned int msr;
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u64 config_mask;
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u64 valid_mask;
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};
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#define EVENT_EXTRA_REG(e, ms, m, vm) { \
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.event = (e), \
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.msr = (ms), \
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.config_mask = (m), \
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.valid_mask = (vm), \
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}
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#define INTEL_EVENT_EXTRA_REG(event, msr, vm) \
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EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm)
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#define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0)
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union perf_capabilities {
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struct {
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u64 lbr_format : 6;
@@ -221,6 +252,7 @@ struct x86_pmu {
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void (*put_event_constraints)(struct cpu_hw_events *cpuc,
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struct perf_event *event);
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struct event_constraint *event_constraints;
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struct event_constraint *percore_constraints;
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void (*quirks)(void);
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int perfctr_second_write;
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@@ -249,6 +281,11 @@ struct x86_pmu {
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*/
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unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */
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int lbr_nr; /* hardware stack size */
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/*
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* Extra registers for events
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*/
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struct extra_reg *extra_regs;
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};
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static struct x86_pmu x86_pmu __read_mostly;
@@ -341,6 +378,31 @@ static inline unsigned int x86_pmu_event_addr(int index)
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return x86_pmu.perfctr + x86_pmu_addr_offset(index);
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}
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/*
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* Find and validate any extra registers to set up.
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*/
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static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
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{
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struct extra_reg *er;
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event->hw.extra_reg = 0;
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event->hw.extra_config = 0;
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if (!x86_pmu.extra_regs)
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return 0;
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for (er = x86_pmu.extra_regs; er->msr; er++) {
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if (er->event != (config & er->config_mask))
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continue;
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if (event->attr.config1 & ~er->valid_mask)
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return -EINVAL;
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event->hw.extra_reg = er->msr;
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event->hw.extra_config = event->attr.config1;
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break;
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}
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return 0;
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}
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static atomic_t active_events;
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static DEFINE_MUTEX(pmc_reserve_mutex);
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@@ -665,6 +727,8 @@ static void x86_pmu_disable(struct pmu *pmu)
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static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
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u64 enable_mask)
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{
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if (hwc->extra_reg)
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wrmsrl(hwc->extra_reg, hwc->extra_config);
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wrmsrl(hwc->config_base, hwc->config | enable_mask);
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}
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