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amlutoIngo Molnar
amluto
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Ingo Molnar
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perf/x86: Add an MSR PMU driver
This patch adds an MSR PMU to support free running MSR counters. Such as time and freq related counters includes TSC, IA32_APERF, IA32_MPERF and IA32_PPERF, but also SMI_COUNT. The events are exposed in sysfs for use by perf stat and other tools. The files are under /sys/devices/msr/events/ Signed-off-by: Andy Lutomirski <luto@kernel.org> Signed-off-by: Kan Liang <kan.liang@intel.com> [ s/freq/msr/, added SMI_COUNT, fixed bugs. ] Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: acme@kernel.org Cc: adrian.hunter@intel.com Cc: dsahern@gmail.com Cc: eranian@google.com Cc: jolsa@kernel.org Cc: mark.rutland@arm.com Cc: namhyung@kernel.org Link: http://lkml.kernel.org/r/1437407346-31186-1-git-send-email-kan.liang@intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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‎arch/x86/kernel/cpu/Makefile

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@@ -46,6 +46,8 @@ obj-$(CONFIG_PERF_EVENTS_INTEL_UNCORE) += perf_event_intel_uncore.o \
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perf_event_intel_uncore_snb.o \
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perf_event_intel_uncore_snbep.o \
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perf_event_intel_uncore_nhmex.o
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obj-$(CONFIG_CPU_SUP_INTEL) += perf_event_msr.o
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obj-$(CONFIG_CPU_SUP_AMD) += perf_event_msr.o
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endif
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‎arch/x86/kernel/cpu/perf_event_msr.c

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#include <linux/perf_event.h>
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enum perf_msr_id {
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PERF_MSR_TSC = 0,
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PERF_MSR_APERF = 1,
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PERF_MSR_MPERF = 2,
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PERF_MSR_PPERF = 3,
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PERF_MSR_SMI = 4,
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PERF_MSR_EVENT_MAX,
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};
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struct perf_msr {
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int id;
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u64 msr;
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};
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static struct perf_msr msr[] = {
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{ PERF_MSR_TSC, 0 },
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{ PERF_MSR_APERF, MSR_IA32_APERF },
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{ PERF_MSR_MPERF, MSR_IA32_MPERF },
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{ PERF_MSR_PPERF, MSR_PPERF },
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{ PERF_MSR_SMI, MSR_SMI_COUNT },
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};
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PMU_EVENT_ATTR_STRING(tsc, evattr_tsc, "event=0x00");
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PMU_EVENT_ATTR_STRING(aperf, evattr_aperf, "event=0x01");
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PMU_EVENT_ATTR_STRING(mperf, evattr_mperf, "event=0x02");
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PMU_EVENT_ATTR_STRING(pperf, evattr_pperf, "event=0x03");
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PMU_EVENT_ATTR_STRING(smi, evattr_smi, "event=0x04");
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static struct attribute *events_attrs[PERF_MSR_EVENT_MAX + 1] = {
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&evattr_tsc.attr.attr,
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};
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static struct attribute_group events_attr_group = {
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.name = "events",
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.attrs = events_attrs,
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};
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PMU_FORMAT_ATTR(event, "config:0-63");
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static struct attribute *format_attrs[] = {
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&format_attr_event.attr,
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NULL,
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};
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static struct attribute_group format_attr_group = {
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.name = "format",
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.attrs = format_attrs,
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};
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static const struct attribute_group *attr_groups[] = {
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&events_attr_group,
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&format_attr_group,
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NULL,
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};
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static int msr_event_init(struct perf_event *event)
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{
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u64 cfg = event->attr.config;
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if (event->attr.type != event->pmu->type)
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return -ENOENT;
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if (cfg >= PERF_MSR_EVENT_MAX)
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return -EINVAL;
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/* unsupported modes and filters */
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if (event->attr.exclude_user ||
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event->attr.exclude_kernel ||
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event->attr.exclude_hv ||
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event->attr.exclude_idle ||
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event->attr.exclude_host ||
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event->attr.exclude_guest ||
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event->attr.sample_period) /* no sampling */
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return -EINVAL;
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event->hw.idx = -1;
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event->hw.event_base = msr[cfg].msr;
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event->hw.config = cfg;
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return 0;
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}
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static inline u64 msr_read_counter(struct perf_event *event)
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{
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u64 now;
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if (event->hw.event_base)
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rdmsrl(event->hw.event_base, now);
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else
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now = rdtsc();
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return now;
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}
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static void msr_event_update(struct perf_event *event)
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{
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u64 prev, now;
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s64 delta;
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/* Careful, an NMI might modify the previous event value. */
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again:
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prev = local64_read(&event->hw.prev_count);
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now = msr_read_counter(event);
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if (local64_cmpxchg(&event->hw.prev_count, prev, now) != prev)
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goto again;
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delta = now - prev;
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if (unlikely(event->hw.event_base == MSR_SMI_COUNT)) {
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delta <<= 32;
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delta >>= 32; /* sign extend */
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}
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local64_add(now - prev, &event->count);
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}
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static void msr_event_start(struct perf_event *event, int flags)
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{
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u64 now;
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now = msr_read_counter(event);
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local64_set(&event->hw.prev_count, now);
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}
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static void msr_event_stop(struct perf_event *event, int flags)
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{
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msr_event_update(event);
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}
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static void msr_event_del(struct perf_event *event, int flags)
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{
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msr_event_stop(event, PERF_EF_UPDATE);
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}
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static int msr_event_add(struct perf_event *event, int flags)
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{
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if (flags & PERF_EF_START)
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msr_event_start(event, flags);
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return 0;
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}
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static struct pmu pmu_msr = {
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.task_ctx_nr = perf_sw_context,
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.attr_groups = attr_groups,
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.event_init = msr_event_init,
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.add = msr_event_add,
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.del = msr_event_del,
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.start = msr_event_start,
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.stop = msr_event_stop,
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.read = msr_event_update,
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.capabilities = PERF_PMU_CAP_NO_INTERRUPT,
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};
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static int __init intel_msr_init(int idx)
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{
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if (boot_cpu_data.x86 != 6)
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return 0;
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switch (boot_cpu_data.x86_model) {
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case 30: /* 45nm Nehalem */
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case 26: /* 45nm Nehalem-EP */
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case 46: /* 45nm Nehalem-EX */
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case 37: /* 32nm Westmere */
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case 44: /* 32nm Westmere-EP */
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case 47: /* 32nm Westmere-EX */
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case 42: /* 32nm SandyBridge */
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case 45: /* 32nm SandyBridge-E/EN/EP */
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case 58: /* 22nm IvyBridge */
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case 62: /* 22nm IvyBridge-EP/EX */
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case 60: /* 22nm Haswell Core */
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case 63: /* 22nm Haswell Server */
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case 69: /* 22nm Haswell ULT */
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case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
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case 61: /* 14nm Broadwell Core-M */
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case 86: /* 14nm Broadwell Xeon D */
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case 71: /* 14nm Broadwell + GT3e (Intel Iris Pro graphics) */
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case 79: /* 14nm Broadwell Server */
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events_attrs[idx++] = &evattr_smi.attr.attr;
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break;
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case 78: /* 14nm Skylake Mobile */
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case 94: /* 14nm Skylake Desktop */
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events_attrs[idx++] = &evattr_pperf.attr.attr;
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events_attrs[idx++] = &evattr_smi.attr.attr;
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break;
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case 55: /* 22nm Atom "Silvermont" */
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case 76: /* 14nm Atom "Airmont" */
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case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */
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events_attrs[idx++] = &evattr_smi.attr.attr;
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break;
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}
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events_attrs[idx] = NULL;
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return 0;
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}
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static int __init amd_msr_init(int idx)
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{
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return 0;
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}
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static int __init msr_init(void)
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{
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int err;
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int idx = 1;
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if (boot_cpu_has(X86_FEATURE_APERFMPERF)) {
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events_attrs[idx++] = &evattr_aperf.attr.attr;
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events_attrs[idx++] = &evattr_mperf.attr.attr;
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events_attrs[idx] = NULL;
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}
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switch (boot_cpu_data.x86_vendor) {
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case X86_VENDOR_INTEL:
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err = intel_msr_init(idx);
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break;
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case X86_VENDOR_AMD:
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err = amd_msr_init(idx);
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break;
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default:
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err = -ENOTSUPP;
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}
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if (err != 0) {
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pr_cont("no msr PMU driver.\n");
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return 0;
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}
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perf_pmu_register(&pmu_msr, "msr", -1);
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return 0;
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}
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device_initcall(msr_init);

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