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Christoffer Dall
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ARM: Add page table and page defines needed by KVM
KVM uses the stage-2 page tables and the Hyp page table format, so we define the fields and page protection flags needed by KVM. The nomenclature is this: - page_hyp: PL2 code/data mappings - page_hyp_device: PL2 device mappings (vgic access) - page_s2: Stage-2 code/data page mappings - page_s2_device: Stage-2 device mappings (vgic access) Reviewed-by: Will Deacon <will.deacon@arm.com> Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com> Christoffer Dall <c.dall@virtualopensystems.com>
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‎arch/arm/include/asm/pgtable-3level.h

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -104,11 +104,29 @@
104104
*/
105105
#define L_PGD_SWAPPER (_AT(pgdval_t, 1) << 55) /* swapper_pg_dir entry */
106106

107+
/*
108+
* 2nd stage PTE definitions for LPAE.
109+
*/
110+
#define L_PTE_S2_MT_UNCACHED (_AT(pteval_t, 0x5) << 2) /* MemAttr[3:0] */
111+
#define L_PTE_S2_MT_WRITETHROUGH (_AT(pteval_t, 0xa) << 2) /* MemAttr[3:0] */
112+
#define L_PTE_S2_MT_WRITEBACK (_AT(pteval_t, 0xf) << 2) /* MemAttr[3:0] */
113+
#define L_PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[1] */
114+
#define L_PTE_S2_RDWR (_AT(pteval_t, 2) << 6) /* HAP[2:1] */
115+
116+
/*
117+
* Hyp-mode PL2 PTE definitions for LPAE.
118+
*/
119+
#define L_PTE_HYP L_PTE_USER
120+
107121
#ifndef __ASSEMBLY__
108122

109123
#define pud_none(pud) (!pud_val(pud))
110124
#define pud_bad(pud) (!(pud_val(pud) & 2))
111125
#define pud_present(pud) (pud_val(pud))
126+
#define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
127+
PMD_TYPE_TABLE)
128+
#define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
129+
PMD_TYPE_SECT)
112130

113131
#define pud_clear(pudp) \
114132
do { \

‎arch/arm/include/asm/pgtable.h

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -70,6 +70,9 @@ extern void __pgd_error(const char *file, int line, pgd_t);
7070

7171
extern pgprot_t pgprot_user;
7272
extern pgprot_t pgprot_kernel;
73+
extern pgprot_t pgprot_hyp_device;
74+
extern pgprot_t pgprot_s2;
75+
extern pgprot_t pgprot_s2_device;
7376

7477
#define _MOD_PROT(p, b) __pgprot(pgprot_val(p) | (b))
7578

@@ -82,6 +85,10 @@ extern pgprot_t pgprot_kernel;
8285
#define PAGE_READONLY_EXEC _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY)
8386
#define PAGE_KERNEL _MOD_PROT(pgprot_kernel, L_PTE_XN)
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#define PAGE_KERNEL_EXEC pgprot_kernel
88+
#define PAGE_HYP _MOD_PROT(pgprot_kernel, L_PTE_HYP)
89+
#define PAGE_HYP_DEVICE _MOD_PROT(pgprot_hyp_device, L_PTE_HYP)
90+
#define PAGE_S2 _MOD_PROT(pgprot_s2, L_PTE_S2_RDONLY)
91+
#define PAGE_S2_DEVICE _MOD_PROT(pgprot_s2_device, L_PTE_USER | L_PTE_S2_RDONLY)
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8693
#define __PAGE_NONE __pgprot(_L_PTE_DEFAULT | L_PTE_RDONLY | L_PTE_XN | L_PTE_NONE)
8794
#define __PAGE_SHARED __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_XN)

‎arch/arm/mm/mmu.c

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -57,6 +57,9 @@ static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
5757
static unsigned int ecc_mask __initdata = 0;
5858
pgprot_t pgprot_user;
5959
pgprot_t pgprot_kernel;
60+
pgprot_t pgprot_hyp_device;
61+
pgprot_t pgprot_s2;
62+
pgprot_t pgprot_s2_device;
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6164
EXPORT_SYMBOL(pgprot_user);
6265
EXPORT_SYMBOL(pgprot_kernel);
@@ -66,34 +69,46 @@ struct cachepolicy {
6669
unsigned int cr_mask;
6770
pmdval_t pmd;
6871
pteval_t pte;
72+
pteval_t pte_s2;
6973
};
7074

75+
#ifdef CONFIG_ARM_LPAE
76+
#define s2_policy(policy) policy
77+
#else
78+
#define s2_policy(policy) 0
79+
#endif
80+
7181
static struct cachepolicy cache_policies[] __initdata = {
7282
{
7383
.policy = "uncached",
7484
.cr_mask = CR_W|CR_C,
7585
.pmd = PMD_SECT_UNCACHED,
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.pte = L_PTE_MT_UNCACHED,
87+
.pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
7788
}, {
7889
.policy = "buffered",
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.cr_mask = CR_C,
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.pmd = PMD_SECT_BUFFERED,
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.pte = L_PTE_MT_BUFFERABLE,
93+
.pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
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}, {
8395
.policy = "writethrough",
8496
.cr_mask = 0,
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.pmd = PMD_SECT_WT,
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.pte = L_PTE_MT_WRITETHROUGH,
99+
.pte_s2 = s2_policy(L_PTE_S2_MT_WRITETHROUGH),
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}, {
88101
.policy = "writeback",
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.cr_mask = 0,
90103
.pmd = PMD_SECT_WB,
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.pte = L_PTE_MT_WRITEBACK,
105+
.pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
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}, {
93107
.policy = "writealloc",
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.cr_mask = 0,
95109
.pmd = PMD_SECT_WBWA,
96110
.pte = L_PTE_MT_WRITEALLOC,
111+
.pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
97112
}
98113
};
99114

@@ -310,6 +325,7 @@ static void __init build_mem_type_table(void)
310325
struct cachepolicy *cp;
311326
unsigned int cr = get_cr();
312327
pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
328+
pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot;
313329
int cpu_arch = cpu_architecture();
314330
int i;
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@@ -421,6 +437,8 @@ static void __init build_mem_type_table(void)
421437
*/
422438
cp = &cache_policies[cachepolicy];
423439
vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
440+
s2_pgprot = cp->pte_s2;
441+
hyp_device_pgprot = s2_device_pgprot = mem_types[MT_DEVICE].prot_pte;
424442

425443
/*
426444
* ARMv6 and above have extended page tables.
@@ -444,6 +462,7 @@ static void __init build_mem_type_table(void)
444462
user_pgprot |= L_PTE_SHARED;
445463
kern_pgprot |= L_PTE_SHARED;
446464
vecs_pgprot |= L_PTE_SHARED;
465+
s2_pgprot |= L_PTE_SHARED;
447466
mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
448467
mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
449468
mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
@@ -498,6 +517,9 @@ static void __init build_mem_type_table(void)
498517
pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
499518
pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
500519
L_PTE_DIRTY | kern_pgprot);
520+
pgprot_s2 = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot);
521+
pgprot_s2_device = __pgprot(s2_device_pgprot);
522+
pgprot_hyp_device = __pgprot(hyp_device_pgprot);
501523

502524
mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
503525
mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;

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