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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk subsystem updates from Stephen Boyd: "We have a fairly balanced mix of clk driver updates and clk framework updates this time around. It's the usual pile of new drivers for new hardware out there and the normal small fixes and updates, but then we have some core framework changes too. In the core framework, we introduce support for a clk_get_optional() API to get clks that may not always be populated and a way to devm manage clkdev lookups registered by provider drivers. We also do some refactoring to simplify the interface between clkdev and the common clk framework so we can reuse the DT parsing and clk_get() path in provider drivers in the future. This work will continue in the next few cycles while we convert how providers specify clk parents. On the driver side, the biggest part of the dirstat is the Amlogic clk driver that got support for the G12A SoC. It dominates with almost half the overall diff, while the second largest part of the diff is in the i.MX clk driver that gained support for imx8mm SoCs. After that, we have the Actions Semiconductor and Qualcomm drivers rounding out the big part of the dirstat because they both got new hardware support for SoCs. The rest is just various updates and non-critical fixes for existing drivers. Core: - Convert a few clk bindings to JSON schema format - Add a {devm_}clk_get_optional() API - Add devm_clk_hw_register_clkdev() API to manage clkdev lookups - Start rewriting clk parent registration and supporting device links by moving around code that supports clk_get() and DT parsing of the 'clocks' property New Drivers: - Add Qualcomm MSM8998 RPM managed clks - IPA clk support on Qualcomm RPMh clk controllers - Actions Semi S500 SoC clk support - Support for fixed rate clks populated from an MMIO register - Add RPC (QSPI/HyperFLASH) clocks on Renesas R-Car V3H - Add TMU (timer) clocks on Renesas RZ/G2E - Add Amlogic G12A Always-On Clock Controller - Add 32k clock generation for Amlogic AXG - Add support for the Mali GPU clocks on Amlogic Meson8 - Add Amlogic G12A EE clock controller driver - Add missing CANFD clocks on Renesas RZ/G2M and RZ/G2E - Add i.MX8MM SoC clk driver support Removed Drivers: - Remove clps711x driver as the board support is gone Updates: - 3rd ECO fix for Mediatek MT2712 SoCs - Updates for Qualcomm MSM8998 GCC clks - Random static analysis fixes for clk drivers - Support for sleeping gpios in the clk-gpio type - Minor fixes for STM32MP1 clk driver (parents, critical flag, etc.) - Split LCDC into two clks on the Marvell MMP2 SoC - Various DT of_node refcount fixes - Get rid of CLK_IS_BASIC from TI code (yay!) - TI Autoidle clk support - Fix Amlogic Meson8 APB clock ID name - Claim input clocks through DT for Amlogic AXG and GXBB - Correct the DU (display unit) parent clock on Renesas RZ/G2E - Exynos5433 IMEM CMU crypto clk support (SlimSS) - Fix for the PLL-MIPI on the Allwinner A23 - Fix Rockchip rk3328 PLL rate calculation - Add SET_RATE_PARENT flag on display clk of Rockhip rk3066 - i.MX SCU clk driver clk_set_parent() and cpufreq support" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (150 commits) dt-bindings: clock: imx8mq: Fix numbering overlaps and gaps clk: ti: clkctrl: Fix clkdm_name regression for TI_CLK_CLKCTRL_COMPAT clk: fixup default index for of_clk_get_by_name() clk: Move of_clk_*() APIs into clk.c from clkdev.c clk: Inform the core about consumer devices clk: Introduce of_clk_get_hw_from_clkspec() clk: core: clarify the check for runtime PM clk: Combine __clk_get() and __clk_create_clk() clk: imx8mq: add GPIO clocks to clock tree clk: mediatek: correct cpu clock name for MT8173 SoC clk: imx: Refactor entire sccg pll clk clk: imx: scu: add cpu frequency scaling support clk: mediatek: Mark bus and DRAM related clocks as critical clk: mediatek: Add flags to mtk_gate clk: mediatek: Add MUX_FLAGS macro clk: qcom: gcc-sdm845: Define parent of PCIe PIPE clocks clk: ingenic: Remove set but not used variable 'enable' clk: at91: programmable: remove unneeded register read clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel clk: mediatek: add MUX_GATE_FLAGS_2 ...
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‎Documentation/devicetree/bindings/clock/actions,owl-cmu.txt

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2,13 +2,14 @@
22

33
The Actions Semi Owl Clock Management Unit generates and supplies clock
44
to various controllers within the SoC. The clock binding described here is
5-
applicable to S900 and S700 SoC's.
5+
applicable to S900, S700 and S500 SoC's.
66

77
Required Properties:
88

99
- compatible: should be one of the following,
1010
"actions,s900-cmu"
1111
"actions,s700-cmu"
12+
"actions,s500-cmu"
1213
- reg: physical base address of the controller and length of memory mapped
1314
region.
1415
- clocks: Reference to the parent clocks ("hosc", "losc")
@@ -19,8 +20,8 @@ Each clock is assigned an identifier, and client nodes can use this identifier
1920
to specify the clock which they consume.
2021

2122
All available clocks are defined as preprocessor macros in corresponding
22-
dt-bindings/clock/actions,s900-cmu.h or actions,s700-cmu.h header and can be
23-
used in device tree sources.
23+
dt-bindings/clock/actions,s900-cmu.h or actions,s700-cmu.h or
24+
actions,s500-cmu.h header and can be used in device tree sources.
2425

2526
External clocks:
2627

‎Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@ Required Properties:
1010
- GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
1111
- GXM (S912) : "amlogic,meson-gxm-aoclkc"
1212
- AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc"
13+
- G12A (S905X2, S905D2, S905Y2) : "amlogic,meson-g12a-aoclkc"
1314
followed by the common "amlogic,meson-gx-aoclkc"
1415
- clocks: list of clock phandle, one for each entry clock-names.
1516
- clock-names: should contain the following:

‎Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@ Required Properties:
99
"amlogic,gxbb-clkc" for GXBB SoC,
1010
"amlogic,gxl-clkc" for GXL and GXM SoC,
1111
"amlogic,axg-clkc" for AXG SoC.
12+
"amlogic,g12a-clkc" for G12A SoC.
1213
- clocks : list of clock phandle, one for each entry clock-names.
1314
- clock-names : should contain the following:
1415
* "xtal": the platform xtal

‎Documentation/devicetree/bindings/clock/exynos5433-clock.txt

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -50,6 +50,8 @@ Required Properties:
5050
IPs.
5151
- "samsung,exynos5433-cmu-cam1" - clock controller compatible for CMU_CAM1
5252
which generates clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs.
53+
- "samsung,exynos5433-cmu-imem" - clock controller compatible for CMU_IMEM
54+
which generates clocks for SSS (Security SubSystem) and SlimSSS IPs.
5355

5456
- reg: physical base address of the controller and length of memory mapped
5557
region.
@@ -168,6 +170,12 @@ Required Properties:
168170
- aclk_cam1_400
169171
- aclk_cam1_552
170172

173+
Input clocks for imem clock controller:
174+
- oscclk
175+
- aclk_imem_sssx_266
176+
- aclk_imem_266
177+
- aclk_imem_200
178+
171179
Optional properties:
172180
- power-domains: a phandle to respective power domain node as described by
173181
generic PM domain bindings (see power/power_domain.txt for more
@@ -469,6 +477,21 @@ Example 2: Examples of clock controller nodes are listed below.
469477
power-domains = <&pd_cam1>;
470478
};
471479

480+
cmu_imem: clock-controller@11060000 {
481+
compatible = "samsung,exynos5433-cmu-imem";
482+
reg = <0x11060000 0x1000>;
483+
#clock-cells = <1>;
484+
485+
clock-names = "oscclk",
486+
"aclk_imem_sssx_266",
487+
"aclk_imem_266",
488+
"aclk_imem_200";
489+
clocks = <&xxti>,
490+
<&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>,
491+
<&cmu_top CLK_DIV_ACLK_IMEM_266>,
492+
<&cmu_top CLK_DIV_ACLK_IMEM_200>;
493+
};
494+
472495
Example 3: UART controller node that consumes the clock generated by the clock
473496
controller.
474497

‎Documentation/devicetree/bindings/clock/fixed-clock.txt

Lines changed: 0 additions & 23 deletions
This file was deleted.

‎Documentation/devicetree/bindings/clock/fixed-clock.yaml

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@@ -0,0 +1,44 @@
1+
# SPDX-License-Identifier: GPL-2.0
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/clock/fixed-clock.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Binding for simple fixed-rate clock sources
8+
9+
maintainers:
10+
- Michael Turquette <mturquette@baylibre.com>
11+
- Stephen Boyd <sboyd@kernel.org>
12+
13+
properties:
14+
compatible:
15+
const: fixed-clock
16+
17+
"#clock-cells":
18+
const: 0
19+
20+
clock-frequency: true
21+
22+
clock-accuracy:
23+
description: accuracy of clock in ppb (parts per billion).
24+
$ref: /schemas/types.yaml#/definitions/uint32
25+
26+
clock-output-names:
27+
maxItems: 1
28+
29+
required:
30+
- compatible
31+
- "#clock-cells"
32+
- clock-frequency
33+
34+
additionalProperties: false
35+
36+
examples:
37+
- |
38+
clock {
39+
compatible = "fixed-clock";
40+
#clock-cells = <0>;
41+
clock-frequency = <1000000000>;
42+
clock-accuracy = <100>;
43+
};
44+
...

‎Documentation/devicetree/bindings/clock/fixed-factor-clock.txt

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This file was deleted.

‎Documentation/devicetree/bindings/clock/fixed-factor-clock.yaml

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@@ -0,0 +1,56 @@
1+
# SPDX-License-Identifier: GPL-2.0
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/clock/fixed-factor-clock.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Binding for simple fixed factor rate clock sources
8+
9+
maintainers:
10+
- Michael Turquette <mturquette@baylibre.com>
11+
- Stephen Boyd <sboyd@kernel.org>
12+
13+
properties:
14+
compatible:
15+
enum:
16+
- allwinner,sun4i-a10-pll3-2x-clk
17+
- fixed-factor-clock
18+
19+
"#clock-cells":
20+
const: 0
21+
22+
clocks:
23+
maxItems: 1
24+
25+
clock-div:
26+
description: Fixed divider
27+
allOf:
28+
- $ref: /schemas/types.yaml#/definitions/uint32
29+
- minimum: 1
30+
31+
clock-mult:
32+
description: Fixed multiplier
33+
$ref: /schemas/types.yaml#/definitions/uint32
34+
35+
clock-output-names:
36+
maxItems: 1
37+
38+
required:
39+
- compatible
40+
- clocks
41+
- "#clock-cells"
42+
- clock-div
43+
- clock-mult
44+
45+
additionalProperties: false
46+
47+
examples:
48+
- |
49+
clock {
50+
compatible = "fixed-factor-clock";
51+
clocks = <&parentclk>;
52+
#clock-cells = <0>;
53+
clock-div = <2>;
54+
clock-mult = <1>;
55+
};
56+
...

‎Documentation/devicetree/bindings/clock/fixed-mmio-clock.txt

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,24 @@
1+
Binding for simple memory mapped io fixed-rate clock sources.
2+
The driver reads a clock frequency value from a single 32-bit memory mapped
3+
I/O register and registers it as a fixed rate clock.
4+
5+
It was designed for test systems, like FPGA, not for complete, finished SoCs.
6+
7+
This binding uses the common clock binding[1].
8+
9+
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
10+
11+
Required properties:
12+
- compatible : shall be "fixed-mmio-clock".
13+
- #clock-cells : from common clock binding; shall be set to 0.
14+
- reg : Address and length of the clock value register set.
15+
16+
Optional properties:
17+
- clock-output-names : From common clock binding.
18+
19+
Example:
20+
sysclock: sysclock@fd020004 {
21+
#clock-cells = <0>;
22+
compatible = "fixed-mmio-clock";
23+
reg = <0xfd020004 0x4>;
24+
};

‎Documentation/devicetree/bindings/clock/imx8mm-clock.txt

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,29 @@
1+
* Clock bindings for NXP i.MX8M Mini
2+
3+
Required properties:
4+
- compatible: Should be "fsl,imx8mm-ccm"
5+
- reg: Address and length of the register set
6+
- #clock-cells: Should be <1>
7+
- clocks: list of clock specifiers, must contain an entry for each required
8+
entry in clock-names
9+
- clock-names: should include the following entries:
10+
- "osc_32k"
11+
- "osc_24m"
12+
- "clk_ext1"
13+
- "clk_ext2"
14+
- "clk_ext3"
15+
- "clk_ext4"
16+
17+
clk: clock-controller@30380000 {
18+
compatible = "fsl,imx8mm-ccm";
19+
reg = <0x0 0x30380000 0x0 0x10000>;
20+
#clock-cells = <1>;
21+
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
22+
<&clk_ext3>, <&clk_ext4>;
23+
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
24+
"clk_ext3", "clk_ext4";
25+
};
26+
27+
The clock consumer should specify the desired clock by having the clock
28+
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mm-clock.h
29+
for the full list of i.MX8M Mini clock IDs.

‎Documentation/devicetree/bindings/clock/qcom,rpmcc.txt

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Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@ Required properties :
1616
"qcom,rpmcc-msm8974", "qcom,rpmcc"
1717
"qcom,rpmcc-apq8064", "qcom,rpmcc"
1818
"qcom,rpmcc-msm8996", "qcom,rpmcc"
19+
"qcom,rpmcc-msm8998", "qcom,rpmcc"
1920
"qcom,rpmcc-qcs404", "qcom,rpmcc"
2021

2122
- #clock-cells : shall contain 1

‎Documentation/driver-model/devres.txt

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Original file line numberDiff line numberDiff line change
@@ -242,9 +242,11 @@ certainly invest a bit more effort into libata core layer).
242242

243243
CLOCK
244244
devm_clk_get()
245+
devm_clk_get_optional()
245246
devm_clk_put()
246247
devm_clk_hw_register()
247248
devm_of_clk_add_hw_provider()
249+
devm_clk_hw_register_clkdev()
248250

249251
DMA
250252
dmaenginem_async_device_register()

‎arch/arm/mach-omap2/omap_hwmod.c

Lines changed: 12 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1002,8 +1002,10 @@ static int _enable_clocks(struct omap_hwmod *oh)
10021002
clk_enable(oh->_clk);
10031003

10041004
list_for_each_entry(os, &oh->slave_ports, node) {
1005-
if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE))
1005+
if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) {
1006+
omap2_clk_deny_idle(os->_clk);
10061007
clk_enable(os->_clk);
1008+
}
10071009
}
10081010

10091011
/* The opt clocks are controlled by the device driver. */
@@ -1055,8 +1057,10 @@ static int _disable_clocks(struct omap_hwmod *oh)
10551057
clk_disable(oh->_clk);
10561058

10571059
list_for_each_entry(os, &oh->slave_ports, node) {
1058-
if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE))
1060+
if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) {
10591061
clk_disable(os->_clk);
1062+
omap2_clk_allow_idle(os->_clk);
1063+
}
10601064
}
10611065

10621066
if (oh->flags & HWMOD_OPT_CLKS_NEEDED)
@@ -2436,9 +2440,13 @@ static void _setup_iclk_autoidle(struct omap_hwmod *oh)
24362440
continue;
24372441

24382442
if (os->flags & OCPIF_SWSUP_IDLE) {
2439-
/* XXX omap_iclk_deny_idle(c); */
2443+
/*
2444+
* we might have multiple users of one iclk with
2445+
* different requirements, disable autoidle when
2446+
* the module is enabled, e.g. dss iclk
2447+
*/
24402448
} else {
2441-
/* XXX omap_iclk_allow_idle(c); */
2449+
/* we are enabling autoidle afterwards anyways */
24422450
clk_enable(os->_clk);
24432451
}
24442452
}

‎drivers/acpi/acpi_lpss.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@
1818
#include <linux/mutex.h>
1919
#include <linux/pci.h>
2020
#include <linux/platform_device.h>
21-
#include <linux/platform_data/clk-lpss.h>
21+
#include <linux/platform_data/x86/clk-lpss.h>
2222
#include <linux/platform_data/x86/pmc_atom.h>
2323
#include <linux/pm_domain.h>
2424
#include <linux/pm_runtime.h>

‎drivers/clk/Kconfig

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -290,6 +290,12 @@ config COMMON_CLK_BD718XX
290290
This driver supports ROHM BD71837 and ROHM BD71847
291291
PMICs clock gates.
292292

293+
config COMMON_CLK_FIXED_MMIO
294+
bool "Clock driver for Memory Mapped Fixed values"
295+
depends on COMMON_CLK && OF
296+
help
297+
Support for Memory Mapped IO Fixed clocks
298+
293299
source "drivers/clk/actions/Kconfig"
294300
source "drivers/clk/bcm/Kconfig"
295301
source "drivers/clk/hisilicon/Kconfig"

‎drivers/clk/Makefile

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o
2727
obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o
2828
obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o
2929
obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o
30+
obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o
3031
obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o
3132
obj-$(CONFIG_COMMON_CLK_ASPEED) += clk-aspeed.o
3233
obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
@@ -78,7 +79,7 @@ obj-$(CONFIG_ARCH_K3) += keystone/
7879
obj-$(CONFIG_ARCH_KEYSTONE) += keystone/
7980
obj-$(CONFIG_MACH_LOONGSON32) += loongson1/
8081
obj-y += mediatek/
81-
obj-$(CONFIG_COMMON_CLK_AMLOGIC) += meson/
82+
obj-$(CONFIG_ARCH_MESON) += meson/
8283
obj-$(CONFIG_MACH_PIC32) += microchip/
8384
ifeq ($(CONFIG_COMMON_CLK), y)
8485
obj-$(CONFIG_ARCH_MMP) += mmp/

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