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Merge tag 'sh-pfc-for-v4.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Updates for v4.14 - Propagate errors on group config, now r8a7740-armadillo800eva.dts is fixed, - Add MSIOF and USB2.0 pin groups on R-Car H3 ES2.0, - Add USB2.0 and USB3.0 pin groups on R-Car M3-W, - Add a missing MMC pin group on R-Car M2-W and RZ/G1M, - Add initial support for R-Car D3, - Small fixes and cleanups.
2 parents 1865af2 + 56d5739 commit dddd966

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10 files changed

+2978
-122
lines changed

10 files changed

+2978
-122
lines changed

Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,7 @@ Required Properties:
2424
- "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller.
2525
- "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller.
2626
- "renesas,pfc-r8a7796": for R8A7796 (R-Car M3-W) compatible pin-controller.
27+
- "renesas,pfc-r8a77995": for R8A77995 (R-Car D3) compatible pin-controller.
2728
- "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
2829

2930
- reg: Base address and length of each memory resource used by the pin

drivers/pinctrl/sh-pfc/Kconfig

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -89,6 +89,11 @@ config PINCTRL_PFC_R8A7796
8989
depends on ARCH_R8A7796
9090
select PINCTRL_SH_PFC
9191

92+
config PINCTRL_PFC_R8A77995
93+
def_bool y
94+
depends on ARCH_R8A77995
95+
select PINCTRL_SH_PFC
96+
9297
config PINCTRL_PFC_SH7203
9398
def_bool y
9499
depends on CPU_SUBTYPE_SH7203

drivers/pinctrl/sh-pfc/Makefile

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o
1515
obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o
1616
obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795-es1.o
1717
obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o
18+
obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
1819
obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o
1920
obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o
2021
obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o

drivers/pinctrl/sh-pfc/core.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -551,6 +551,12 @@ static const struct of_device_id sh_pfc_of_table[] = {
551551
.data = &r8a7796_pinmux_info,
552552
},
553553
#endif
554+
#ifdef CONFIG_PINCTRL_PFC_R8A77995
555+
{
556+
.compatible = "renesas,pfc-r8a77995",
557+
.data = &r8a77995_pinmux_info,
558+
},
559+
#endif
554560
#ifdef CONFIG_PINCTRL_PFC_SH73A0
555561
{
556562
.compatible = "renesas,pfc-sh73a0",

drivers/pinctrl/sh-pfc/pfc-r8a7791.c

Lines changed: 14 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2589,6 +2589,17 @@ static const unsigned int mmc_data8_mux[] = {
25892589
MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
25902590
MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
25912591
};
2592+
static const unsigned int mmc_data8_b_pins[] = {
2593+
/* D[0:7] */
2594+
RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2595+
RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2596+
RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2597+
RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
2598+
};
2599+
static const unsigned int mmc_data8_b_mux[] = {
2600+
MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2601+
MMC_D4_MARK, MMC_D5_MARK, MMC_D6_B_MARK, MMC_D7_B_MARK,
2602+
};
25922603
static const unsigned int mmc_ctrl_pins[] = {
25932604
/* CLK, CMD */
25942605
RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
@@ -4420,7 +4431,7 @@ static const unsigned int vin2_clk_mux[] = {
44204431
};
44214432

44224433
static const struct {
4423-
struct sh_pfc_pin_group common[341];
4434+
struct sh_pfc_pin_group common[342];
44244435
struct sh_pfc_pin_group r8a779x[9];
44254436
} pinmux_groups = {
44264437
.common = {
@@ -4523,6 +4534,7 @@ static const struct {
45234534
SH_PFC_PIN_GROUP(mmc_data1),
45244535
SH_PFC_PIN_GROUP(mmc_data4),
45254536
SH_PFC_PIN_GROUP(mmc_data8),
4537+
SH_PFC_PIN_GROUP(mmc_data8_b),
45264538
SH_PFC_PIN_GROUP(mmc_ctrl),
45274539
SH_PFC_PIN_GROUP(msiof0_clk),
45284540
SH_PFC_PIN_GROUP(msiof0_sync),
@@ -4955,6 +4967,7 @@ static const char * const mmc_groups[] = {
49554967
"mmc_data1",
49564968
"mmc_data4",
49574969
"mmc_data8",
4970+
"mmc_data8_b",
49584971
"mmc_ctrl",
49594972
};
49604973

drivers/pinctrl/sh-pfc/pfc-r8a7795.c

Lines changed: 1024 additions & 58 deletions
Large diffs are not rendered by default.

drivers/pinctrl/sh-pfc/pfc-r8a7796.c

Lines changed: 91 additions & 55 deletions
Large diffs are not rendered by default.

drivers/pinctrl/sh-pfc/pfc-r8a77995.c

Lines changed: 1812 additions & 0 deletions
Large diffs are not rendered by default.

drivers/pinctrl/sh-pfc/pinctrl.c

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -742,13 +742,16 @@ static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
742742
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
743743
const unsigned int *pins;
744744
unsigned int num_pins;
745-
unsigned int i;
745+
unsigned int i, ret;
746746

747747
pins = pmx->pfc->info->groups[group].pins;
748748
num_pins = pmx->pfc->info->groups[group].nr_pins;
749749

750-
for (i = 0; i < num_pins; ++i)
751-
sh_pfc_pinconf_set(pctldev, pins[i], configs, num_configs);
750+
for (i = 0; i < num_pins; ++i) {
751+
ret = sh_pfc_pinconf_set(pctldev, pins[i], configs, num_configs);
752+
if (ret)
753+
return ret;
754+
}
752755

753756
return 0;
754757
}

drivers/pinctrl/sh-pfc/sh_pfc.h

Lines changed: 18 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -271,6 +271,7 @@ extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
271271
extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
272272
extern const struct sh_pfc_soc_info r8a7795es1_pinmux_info;
273273
extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
274+
extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
274275
extern const struct sh_pfc_soc_info sh7203_pinmux_info;
275276
extern const struct sh_pfc_soc_info sh7264_pinmux_info;
276277
extern const struct sh_pfc_soc_info sh7269_pinmux_info;
@@ -389,9 +390,13 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
389390
PORT_GP_CFG_1(bank, 8, fn, sfx, cfg)
390391
#define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0)
391392

392-
#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \
393+
#define PORT_GP_CFG_10(bank, fn, sfx, cfg) \
393394
PORT_GP_CFG_9(bank, fn, sfx, cfg), \
394-
PORT_GP_CFG_1(bank, 9, fn, sfx, cfg), \
395+
PORT_GP_CFG_1(bank, 9, fn, sfx, cfg)
396+
#define PORT_GP_10(bank, fn, sfx) PORT_GP_CFG_10(bank, fn, sfx, 0)
397+
398+
#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \
399+
PORT_GP_CFG_10(bank, fn, sfx, cfg), \
395400
PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), \
396401
PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
397402
#define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0)
@@ -422,11 +427,19 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
422427
PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
423428
#define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0)
424429

425-
#define PORT_GP_CFG_23(bank, fn, sfx, cfg) \
430+
#define PORT_GP_CFG_20(bank, fn, sfx, cfg) \
426431
PORT_GP_CFG_18(bank, fn, sfx, cfg), \
427432
PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \
428-
PORT_GP_CFG_1(bank, 19, fn, sfx, cfg), \
429-
PORT_GP_CFG_1(bank, 20, fn, sfx, cfg), \
433+
PORT_GP_CFG_1(bank, 19, fn, sfx, cfg)
434+
#define PORT_GP_20(bank, fn, sfx) PORT_GP_CFG_20(bank, fn, sfx, 0)
435+
436+
#define PORT_GP_CFG_21(bank, fn, sfx, cfg) \
437+
PORT_GP_CFG_20(bank, fn, sfx, cfg), \
438+
PORT_GP_CFG_1(bank, 20, fn, sfx, cfg)
439+
#define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0)
440+
441+
#define PORT_GP_CFG_23(bank, fn, sfx, cfg) \
442+
PORT_GP_CFG_21(bank, fn, sfx, cfg), \
430443
PORT_GP_CFG_1(bank, 21, fn, sfx, cfg), \
431444
PORT_GP_CFG_1(bank, 22, fn, sfx, cfg)
432445
#define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0)

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