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Like XuPeter Zijlstra
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perf/x86/core: Completely disable guest PEBS via guest's global_ctrl
When a guest PEBS counter is cross-mapped by a host counter, software will remove the corresponding bit in the arr[global_ctrl].guest and expect hardware to perform a change of state "from enable to disable" via the msr_slot[] switch during the vmx transaction. The real world is that if user adjust the counter overflow value small enough, it still opens a tiny race window for the previously PEBS-enabled counter to write cross-mapped PEBS records into the guest's PEBS buffer, when arr[global_ctrl].guest has been prioritised (switch_msr_special stuff) to switch into the enabled state, while the arr[pebs_enable].guest has not. Close this window by clearing invalid bits in the arr[global_ctrl].guest. Fixes: 8542503 ("KVM: x86/pmu: Disable guest PEBS temporarily in two rare situations") Signed-off-by: Like Xu <likexu@tencent.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/20220831033524.58561-1-likexu@tencent.com
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arch/x86/events/intel/core.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4061,8 +4061,9 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data)
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/* Disable guest PEBS if host PEBS is enabled. */
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arr[pebs_enable].guest = 0;
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} else {
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/* Disable guest PEBS for cross-mapped PEBS counters. */
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/* Disable guest PEBS thoroughly for cross-mapped PEBS counters. */
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arr[pebs_enable].guest &= ~kvm_pmu->host_cross_mapped_mask;
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arr[global_ctrl].guest &= ~kvm_pmu->host_cross_mapped_mask;
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/* Set hw GLOBAL_CTRL bits for PEBS counter when it runs for guest */
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arr[global_ctrl].guest |= arr[pebs_enable].guest;
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}

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