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ludovicbarreMarc Zyngier
ludovicbarre
authored and
Marc Zyngier
committed
irqchip/stm32: Add host and driver data structures
This patch adds host and driver data structures to support different stm32 exti controllers with variants. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
1 parent d9e2b19 commit f9fc174

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-48
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+104
-48
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‎drivers/irqchip/irq-stm32-exti.c

Lines changed: 104 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -29,13 +29,23 @@ struct stm32_exti_bank {
2929

3030
#define UNDEF_REG ~0
3131

32+
struct stm32_exti_drv_data {
33+
const struct stm32_exti_bank **exti_banks;
34+
u32 bank_nr;
35+
};
36+
3237
struct stm32_exti_chip_data {
38+
struct stm32_exti_host_data *host_data;
3339
const struct stm32_exti_bank *reg_bank;
3440
u32 rtsr_cache;
3541
u32 ftsr_cache;
3642
};
3743

38-
static struct stm32_exti_chip_data *stm32_exti_data;
44+
struct stm32_exti_host_data {
45+
void __iomem *base;
46+
struct stm32_exti_chip_data *chips_data;
47+
const struct stm32_exti_drv_data *drv_data;
48+
};
3949

4050
static const struct stm32_exti_bank stm32f4xx_exti_b1 = {
4151
.imr_ofst = 0x00,
@@ -51,6 +61,11 @@ static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = {
5161
&stm32f4xx_exti_b1,
5262
};
5363

64+
static const struct stm32_exti_drv_data stm32f4xx_drv_data = {
65+
.exti_banks = stm32f4xx_exti_banks,
66+
.bank_nr = ARRAY_SIZE(stm32f4xx_exti_banks),
67+
};
68+
5469
static const struct stm32_exti_bank stm32h7xx_exti_b1 = {
5570
.imr_ofst = 0x80,
5671
.emr_ofst = 0x84,
@@ -87,6 +102,11 @@ static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = {
87102
&stm32h7xx_exti_b3,
88103
};
89104

105+
static const struct stm32_exti_drv_data stm32h7xx_drv_data = {
106+
.exti_banks = stm32h7xx_exti_banks,
107+
.bank_nr = ARRAY_SIZE(stm32h7xx_exti_banks),
108+
};
109+
90110
static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
91111
{
92112
struct stm32_exti_chip_data *chip_data = gc->private;
@@ -237,29 +257,85 @@ static void stm32_irq_ack(struct irq_data *d)
237257

238258
irq_gc_unlock(gc);
239259
}
260+
static struct
261+
stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd,
262+
struct device_node *node)
263+
{
264+
struct stm32_exti_host_data *host_data;
265+
266+
host_data = kzalloc(sizeof(*host_data), GFP_KERNEL);
267+
if (!host_data)
268+
return NULL;
269+
270+
host_data->drv_data = dd;
271+
host_data->chips_data = kcalloc(dd->bank_nr,
272+
sizeof(struct stm32_exti_chip_data),
273+
GFP_KERNEL);
274+
if (!host_data->chips_data)
275+
return NULL;
276+
277+
host_data->base = of_iomap(node, 0);
278+
if (!host_data->base) {
279+
pr_err("%pOF: Unable to map registers\n", node);
280+
return NULL;
281+
}
240282

241-
static int
242-
__init stm32_exti_init(const struct stm32_exti_bank **stm32_exti_banks,
243-
int bank_nr, struct device_node *node)
283+
return host_data;
284+
}
285+
286+
static struct
287+
stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data,
288+
u32 bank_idx,
289+
struct device_node *node)
290+
{
291+
const struct stm32_exti_bank *stm32_bank;
292+
struct stm32_exti_chip_data *chip_data;
293+
void __iomem *base = h_data->base;
294+
u32 irqs_mask;
295+
296+
stm32_bank = h_data->drv_data->exti_banks[bank_idx];
297+
chip_data = &h_data->chips_data[bank_idx];
298+
chip_data->host_data = h_data;
299+
chip_data->reg_bank = stm32_bank;
300+
301+
/* Determine number of irqs supported */
302+
writel_relaxed(~0UL, base + stm32_bank->rtsr_ofst);
303+
irqs_mask = readl_relaxed(base + stm32_bank->rtsr_ofst);
304+
305+
/*
306+
* This IP has no reset, so after hot reboot we should
307+
* clear registers to avoid residue
308+
*/
309+
writel_relaxed(0, base + stm32_bank->imr_ofst);
310+
writel_relaxed(0, base + stm32_bank->emr_ofst);
311+
writel_relaxed(0, base + stm32_bank->rtsr_ofst);
312+
writel_relaxed(0, base + stm32_bank->ftsr_ofst);
313+
writel_relaxed(~0UL, base + stm32_bank->rpr_ofst);
314+
if (stm32_bank->fpr_ofst != UNDEF_REG)
315+
writel_relaxed(~0UL, base + stm32_bank->fpr_ofst);
316+
317+
pr_info("%s: bank%d, External IRQs available:%#x\n",
318+
node->full_name, bank_idx, irqs_mask);
319+
320+
return chip_data;
321+
}
322+
323+
static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data,
324+
struct device_node *node)
244325
{
326+
struct stm32_exti_host_data *host_data;
245327
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
246-
int nr_irqs, nr_exti, ret, i;
328+
int nr_irqs, ret, i;
247329
struct irq_chip_generic *gc;
248330
struct irq_domain *domain;
249-
void *base;
250331

251-
base = of_iomap(node, 0);
252-
if (!base) {
253-
pr_err("%pOF: Unable to map registers\n", node);
254-
return -ENOMEM;
332+
host_data = stm32_exti_host_init(drv_data, node);
333+
if (!host_data) {
334+
ret = -ENOMEM;
335+
goto out_free_mem;
255336
}
256337

257-
stm32_exti_data = kcalloc(bank_nr, sizeof(*stm32_exti_data),
258-
GFP_KERNEL);
259-
if (!stm32_exti_data)
260-
return -ENOMEM;
261-
262-
domain = irq_domain_add_linear(node, bank_nr * IRQS_PER_BANK,
338+
domain = irq_domain_add_linear(node, drv_data->bank_nr * IRQS_PER_BANK,
263339
&irq_exti_domain_ops, NULL);
264340
if (!domain) {
265341
pr_err("%s: Could not register interrupt domain.\n",
@@ -276,16 +352,16 @@ __init stm32_exti_init(const struct stm32_exti_bank **stm32_exti_banks,
276352
goto out_free_domain;
277353
}
278354

279-
for (i = 0; i < bank_nr; i++) {
280-
const struct stm32_exti_bank *stm32_bank = stm32_exti_banks[i];
281-
struct stm32_exti_chip_data *chip_data = &stm32_exti_data[i];
282-
u32 irqs_mask;
355+
for (i = 0; i < drv_data->bank_nr; i++) {
356+
const struct stm32_exti_bank *stm32_bank;
357+
struct stm32_exti_chip_data *chip_data;
283358

284-
chip_data->reg_bank = stm32_bank;
359+
stm32_bank = drv_data->exti_banks[i];
360+
chip_data = stm32_exti_chip_init(host_data, i, node);
285361

286362
gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK);
287363

288-
gc->reg_base = base;
364+
gc->reg_base = host_data->base;
289365
gc->chip_types->type = IRQ_TYPE_EDGE_BOTH;
290366
gc->chip_types->chip.irq_ack = stm32_irq_ack;
291367
gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit;
@@ -298,26 +374,6 @@ __init stm32_exti_init(const struct stm32_exti_bank **stm32_exti_banks,
298374

299375
gc->chip_types->regs.mask = stm32_bank->imr_ofst;
300376
gc->private = (void *)chip_data;
301-
302-
/* Determine number of irqs supported */
303-
writel_relaxed(~0UL, base + stm32_bank->rtsr_ofst);
304-
irqs_mask = readl_relaxed(base + stm32_bank->rtsr_ofst);
305-
nr_exti = fls(readl_relaxed(base + stm32_bank->rtsr_ofst));
306-
307-
/*
308-
* This IP has no reset, so after hot reboot we should
309-
* clear registers to avoid residue
310-
*/
311-
writel_relaxed(0, base + stm32_bank->imr_ofst);
312-
writel_relaxed(0, base + stm32_bank->emr_ofst);
313-
writel_relaxed(0, base + stm32_bank->rtsr_ofst);
314-
writel_relaxed(0, base + stm32_bank->ftsr_ofst);
315-
writel_relaxed(~0UL, base + stm32_bank->rpr_ofst);
316-
if (stm32_bank->fpr_ofst != UNDEF_REG)
317-
writel_relaxed(~0UL, base + stm32_bank->fpr_ofst);
318-
319-
pr_info("%s: bank%d, External IRQs available:%#x\n",
320-
node->full_name, i, irqs_mask);
321377
}
322378

323379
nr_irqs = of_irq_count(node);
@@ -333,25 +389,25 @@ __init stm32_exti_init(const struct stm32_exti_bank **stm32_exti_banks,
333389
out_free_domain:
334390
irq_domain_remove(domain);
335391
out_unmap:
336-
iounmap(base);
337-
kfree(stm32_exti_data);
392+
iounmap(host_data->base);
393+
out_free_mem:
394+
kfree(host_data->chips_data);
395+
kfree(host_data);
338396
return ret;
339397
}
340398

341399
static int __init stm32f4_exti_of_init(struct device_node *np,
342400
struct device_node *parent)
343401
{
344-
return stm32_exti_init(stm32f4xx_exti_banks,
345-
ARRAY_SIZE(stm32f4xx_exti_banks), np);
402+
return stm32_exti_init(&stm32f4xx_drv_data, np);
346403
}
347404

348405
IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init);
349406

350407
static int __init stm32h7_exti_of_init(struct device_node *np,
351408
struct device_node *parent)
352409
{
353-
return stm32_exti_init(stm32h7xx_exti_banks,
354-
ARRAY_SIZE(stm32h7xx_exti_banks), np);
410+
return stm32_exti_init(&stm32h7xx_drv_data, np);
355411
}
356412

357413
IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init);

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