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bebarinobebarino
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Merge branches 'clk-typo', 'clk-json-schema', 'clk-mtk-2712-eco' and 'clk-rockchip' into clk-next
 - Convert a few clk bindings to JSON schema format - 3rd ECO fix for Mediatek MT2712 SoCs * clk-typo: clk: samsung: fix typo * clk-json-schema: dt-bindings: clock: Convert fixed-factor-clock to json-schema dt-bindings: clock: Convert fixed-clock binding to json-schema * clk-mtk-2712-eco: clk: mediatek: update clock driver of MT2712 dt-bindings: clock: add clock for MT2712 * clk-rockchip: clk: rockchip: add CLK_SET_RATE_PARENT for rk3066 lcdc dclks clk: rockchip: fix frac settings of GPLL clock for rk3328
5 parents bd5e2ea + 463a554 + f79bae1 + 51ff86d + a49ba41 commit fea0b08

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9 files changed

+117
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lines changed

‎Documentation/devicetree/bindings/clock/fixed-clock.txt

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This file was deleted.

‎Documentation/devicetree/bindings/clock/fixed-clock.yaml

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,44 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/fixed-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Binding for simple fixed-rate clock sources
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maintainers:
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- Michael Turquette <mturquette@baylibre.com>
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- Stephen Boyd <sboyd@kernel.org>
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properties:
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compatible:
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const: fixed-clock
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"#clock-cells":
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const: 0
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clock-frequency: true
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clock-accuracy:
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description: accuracy of clock in ppb (parts per billion).
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$ref: /schemas/types.yaml#/definitions/uint32
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clock-output-names:
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maxItems: 1
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required:
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- compatible
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- "#clock-cells"
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- clock-frequency
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additionalProperties: false
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examples:
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- |
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clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <1000000000>;
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clock-accuracy = <100>;
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};
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...

‎Documentation/devicetree/bindings/clock/fixed-factor-clock.txt

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This file was deleted.

‎Documentation/devicetree/bindings/clock/fixed-factor-clock.yaml

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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/fixed-factor-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Binding for simple fixed factor rate clock sources
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maintainers:
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- Michael Turquette <mturquette@baylibre.com>
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- Stephen Boyd <sboyd@kernel.org>
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properties:
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compatible:
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enum:
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- allwinner,sun4i-a10-pll3-2x-clk
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- fixed-factor-clock
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"#clock-cells":
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const: 0
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clocks:
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maxItems: 1
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clock-div:
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description: Fixed divider
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32
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- minimum: 1
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clock-mult:
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description: Fixed multiplier
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$ref: /schemas/types.yaml#/definitions/uint32
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clock-output-names:
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maxItems: 1
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required:
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- compatible
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- clocks
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- "#clock-cells"
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- clock-div
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- clock-mult
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additionalProperties: false
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examples:
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- |
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clock {
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compatible = "fixed-factor-clock";
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clocks = <&parentclk>;
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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};
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...

‎drivers/clk/mediatek/clk-mt2712.c

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -223,6 +223,8 @@ static const struct mtk_fixed_factor top_divs[] = {
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4),
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FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1_ck", 1,
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3),
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FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2_ck", 1,
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3),
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};
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228230
static const char * const axi_parents[] = {
@@ -594,15 +596,17 @@ static const char * const a1sys_hp_parents[] = {
594596
"apll1_ck",
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"apll1_d2",
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"apll1_d4",
597-
"apll1_d8"
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"apll1_d8",
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"apll1_d3"
598601
};
599602

600603
static const char * const a2sys_hp_parents[] = {
601604
"clk26m",
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"apll2_ck",
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"apll2_d2",
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"apll2_d4",
605-
"apll2_d8"
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"apll2_d8",
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"apll2_d3"
606610
};
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608612
static const char * const asm_l_parents[] = {

‎drivers/clk/rockchip/clk-rk3188.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -586,12 +586,12 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
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COMPOSITE(0, "dclk_lcdc0_src", mux_pll_src_cpll_gpll_p, 0,
587587
RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS,
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RK2928_CLKGATE_CON(3), 1, GFLAGS),
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MUX(DCLK_LCDC0, "dclk_lcdc0", mux_rk3066_lcdc0_p, 0,
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MUX(DCLK_LCDC0, "dclk_lcdc0", mux_rk3066_lcdc0_p, CLK_SET_RATE_PARENT,
590590
RK2928_CLKSEL_CON(27), 4, 1, MFLAGS),
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COMPOSITE(0, "dclk_lcdc1_src", mux_pll_src_cpll_gpll_p, 0,
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RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS,
593593
RK2928_CLKGATE_CON(3), 2, GFLAGS),
594-
MUX(DCLK_LCDC1, "dclk_lcdc1", mux_rk3066_lcdc1_p, 0,
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MUX(DCLK_LCDC1, "dclk_lcdc1", mux_rk3066_lcdc1_p, CLK_SET_RATE_PARENT,
595595
RK2928_CLKSEL_CON(28), 4, 1, MFLAGS),
596596

597597
COMPOSITE_NOMUX(0, "cif1_pre", "cif_src", 0,

‎drivers/clk/rockchip/clk-rk3328.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -78,17 +78,17 @@ static struct rockchip_pll_rate_table rk3328_pll_rates[] = {
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7979
static struct rockchip_pll_rate_table rk3328_pll_frac_rates[] = {
8080
/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
81-
RK3036_PLL_RATE(1016064000, 3, 127, 1, 1, 0, 134217),
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RK3036_PLL_RATE(1016064000, 3, 127, 1, 1, 0, 134218),
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/* vco = 1016064000 */
83-
RK3036_PLL_RATE(983040000, 24, 983, 1, 1, 0, 671088),
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RK3036_PLL_RATE(983040000, 24, 983, 1, 1, 0, 671089),
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/* vco = 983040000 */
85-
RK3036_PLL_RATE(491520000, 24, 983, 2, 1, 0, 671088),
85+
RK3036_PLL_RATE(491520000, 24, 983, 2, 1, 0, 671089),
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/* vco = 983040000 */
87-
RK3036_PLL_RATE(61440000, 6, 215, 7, 2, 0, 671088),
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RK3036_PLL_RATE(61440000, 6, 215, 7, 2, 0, 671089),
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/* vco = 860156000 */
89-
RK3036_PLL_RATE(56448000, 12, 451, 4, 4, 0, 9797894),
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RK3036_PLL_RATE(56448000, 12, 451, 4, 4, 0, 9797895),
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/* vco = 903168000 */
91-
RK3036_PLL_RATE(40960000, 12, 409, 4, 5, 0, 10066329),
91+
RK3036_PLL_RATE(40960000, 12, 409, 4, 5, 0, 10066330),
9292
/* vco = 819200000 */
9393
{ /* sentinel */ },
9494
};

‎drivers/clk/samsung/clk.h

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@@ -26,7 +26,7 @@ struct samsung_clk_provider {
2626
void __iomem *reg_base;
2727
struct device *dev;
2828
spinlock_t lock;
29-
/* clk_data must be the last entry due to variable lenght 'hws' array */
29+
/* clk_data must be the last entry due to variable length 'hws' array */
3030
struct clk_hw_onecell_data clk_data;
3131
};
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‎include/dt-bindings/clock/mt2712-clk.h

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@@ -228,7 +228,8 @@
228228
#define CLK_TOP_NFI2X_EN 189
229229
#define CLK_TOP_NFIECC_EN 190
230230
#define CLK_TOP_NFI1X_CK_EN 191
231-
#define CLK_TOP_NR_CLK 192
231+
#define CLK_TOP_APLL2_D3 192
232+
#define CLK_TOP_NR_CLK 193
232233

233234
/* INFRACFG */
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