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Commit 1b837b8

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Espressif Systems
committed
update uart driver
1 parent 0255463 commit 1b837b8

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2 files changed

+369
-73
lines changed

2 files changed

+369
-73
lines changed

‎examples/driver_lib/driver/uart.c

+258-8
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,6 @@ typedef struct _os_event_ {
2121
uint32 param;
2222
} os_event_t;
2323

24-
2524
xTaskHandle xUartTaskHandle;
2625
xQueueHandle xQueueUart;
2726

@@ -52,7 +51,20 @@ uart1_write_char(char c)
5251
}
5352
}
5453

55-
LOCAL void uart_rx_intr_handler_ssc(void)
54+
LOCAL void
55+
uart0_write_char(char c)
56+
{
57+
if (c == '\n') {
58+
uart_tx_one_char(UART0, '\r');
59+
uart_tx_one_char(UART0, '\n');
60+
} else if (c == '\r') {
61+
} else {
62+
uart_tx_one_char(UART0, c);
63+
}
64+
}
65+
66+
LOCAL void
67+
uart_rx_intr_handler_ssc(void)
5668
{
5769
/* uart0 and uart1 intr combine togther, when interrupt occur, see reg 0x3ff20020, bit2, bit0 represents
5870
* uart1 and uart0 respectively
@@ -78,6 +90,7 @@ LOCAL void uart_rx_intr_handler_ssc(void)
7890
portEND_SWITCHING_ISR(xHigherPriorityTaskWoken);
7991
}
8092

93+
#if 0
8194
LOCAL void ICACHE_FLASH_ATTR
8295
uart_config(uint8 uart_no, UartDevice *uart)
8396
{
@@ -115,6 +128,7 @@ uart_config(uint8 uart_no, UartDevice *uart)
115128
//enable rx_interrupt
116129
SET_PERI_REG_MASK(UART_INT_ENA(uart_no), UART_RXFIFO_FULL_INT_ENA);
117130
}
131+
#endif
118132

119133
LOCAL void ICACHE_FLASH_ATTR
120134
uart_task(void *pvParameters)
@@ -137,20 +151,22 @@ uart_task(void *pvParameters)
137151
vTaskDelete(NULL);
138152
}
139153

154+
#if 0
140155
void ICACHE_FLASH_ATTR
141156
uart_init(void)
142157
{
143158
while (READ_PERI_REG(UART_STATUS(0)) & (UART_TXFIFO_CNT << UART_TXFIFO_CNT_S));
159+
144160
while (READ_PERI_REG(UART_STATUS(1)) & (UART_TXFIFO_CNT << UART_TXFIFO_CNT_S));
145161

146-
UartDevice uart;
162+
UART_ConfigTypeDef uart;
147163

148164
uart.baut_rate = BIT_RATE_74880;
149-
uart.data_bits = EIGHT_BITS;
150-
uart.flow_ctrl = NONE_CTRL;
151-
uart.exist_parity = STICK_PARITY_DIS;
152-
uart.parity = NONE_BITS;
153-
uart.stop_bits = ONE_STOP_BIT;
165+
uart.data_bits = UART_WordLength_8b;
166+
uart.flow_ctrl = USART_HardwareFlowControl_None;
167+
// uart.exist_parity = PARITY_DIS;
168+
uart.parity = USART_Parity_None;
169+
uart.stop_bits = USART_StopBits_1;
154170

155171
uart_config(UART0, &uart);
156172
uart_config(UART1, &uart);
@@ -163,4 +179,238 @@ uart_init(void)
163179

164180
xTaskCreate(uart_task, (uint8 const *)"uTask", 512, NULL, tskIDLE_PRIORITY + 2, &xUartTaskHandle);
165181
}
182+
#endif
183+
184+
//=================================================================
185+
186+
void ICACHE_FLASH_ATTR
187+
UART_SetWordLength(UART_Port uart_no, UART_WordLength len)
188+
{
189+
SET_PERI_REG_BITS(UART_CONF0(uart_no), UART_BIT_NUM, len, UART_BIT_NUM_S);
190+
}
191+
192+
void ICACHE_FLASH_ATTR
193+
UART_SetStopBits(UART_Port uart_no, UART_StopBits bit_num)
194+
{
195+
SET_PERI_REG_BITS(UART_CONF0(uart_no), UART_STOP_BIT_NUM, bit_num, UART_STOP_BIT_NUM_S);
196+
}
197+
198+
void ICACHE_FLASH_ATTR
199+
UART_SetLineInverse(UART_Port uart_no, UART_LineLevelInverse inverse_mask)
200+
{
201+
CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_LINE_INV_MASK);
202+
SET_PERI_REG_MASK(UART_CONF0(uart_no), inverse_mask);
203+
}
204+
205+
void ICACHE_FLASH_ATTR
206+
UART_SetParity(UART_Port uart_no, UART_ParityMode Parity_mode)
207+
{
208+
CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_PARITY | UART_PARITY_EN);
209+
210+
if (Parity_mode == USART_Parity_None) {
211+
} else {
212+
SET_PERI_REG_MASK(UART_CONF0(uart_no), Parity_mode | UART_PARITY_EN);
213+
}
214+
}
215+
216+
void ICACHE_FLASH_ATTR
217+
UART_SetBaudrate(UART_Port uart_no, uint32 baud_rate)
218+
{
219+
uart_div_modify(uart_no, UART_CLK_FREQ / baud_rate);
220+
}
221+
222+
//only when USART_HardwareFlowControl_RTS is set , will the rx_thresh value be set.
223+
void ICACHE_FLASH_ATTR
224+
UART_SetFlowCtrl(UART_Port uart_no, UART_HwFlowCtrl flow_ctrl, uint8 rx_thresh)
225+
{
226+
if (flow_ctrl & USART_HardwareFlowControl_RTS) {
227+
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, FUNC_U0RTS);
228+
SET_PERI_REG_BITS(UART_CONF1(uart_no), UART_RX_FLOW_THRHD, rx_thresh, UART_RX_FLOW_THRHD_S);
229+
SET_PERI_REG_MASK(UART_CONF1(uart_no), UART_RX_FLOW_EN);
230+
} else {
231+
CLEAR_PERI_REG_MASK(UART_CONF1(uart_no), UART_RX_FLOW_EN);
232+
}
233+
234+
if (flow_ctrl & USART_HardwareFlowControl_CTS) {
235+
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, FUNC_UART0_CTS);
236+
SET_PERI_REG_MASK(UART_CONF0(uart_no), UART_TX_FLOW_EN);
237+
} else {
238+
CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_TX_FLOW_EN);
239+
}
240+
}
241+
242+
void ICACHE_FLASH_ATTR
243+
UART_WaitTxFifoEmpty(UART_Port uart_no) //do not use if tx flow control enabled
244+
{
245+
while (READ_PERI_REG(UART_STATUS(uart_no)) & (UART_TXFIFO_CNT << UART_TXFIFO_CNT_S));
246+
}
247+
248+
void ICACHE_FLASH_ATTR
249+
UART_ResetFifo(UART_Port uart_no)
250+
{
251+
SET_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST | UART_TXFIFO_RST);
252+
CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST | UART_TXFIFO_RST);
253+
}
254+
255+
void ICACHE_FLASH_ATTR
256+
UART_ClearIntrStatus(UART_Port uart_no, uint32 clr_mask)
257+
{
258+
WRITE_PERI_REG(UART_INT_CLR(uart_no), clr_mask);
259+
}
260+
261+
void ICACHE_FLASH_ATTR
262+
UART_SetIntrEna(UART_Port uart_no, uint32 ena_mask)
263+
{
264+
SET_PERI_REG_MASK(UART_INT_ENA(uart_no), ena_mask);
265+
}
266+
267+
void ICACHE_FLASH_ATTR
268+
UART_intr_handler_register(void *fn)
269+
{
270+
_xt_isr_attach(ETS_UART_INUM, fn);
271+
}
272+
273+
void ICACHE_FLASH_ATTR
274+
UART_SetPrintPort(UART_Port uart_no)
275+
{
276+
if (uart_no == 1) {
277+
os_install_putc1(uart1_write_char);
278+
} else {
279+
os_install_putc1(uart0_write_char);
280+
}
281+
}
282+
283+
void ICACHE_FLASH_ATTR
284+
UART_ParamConfig(UART_Port uart_no, UART_ConfigTypeDef *pUARTConfig)
285+
{
286+
if (uart_no == UART1) {
287+
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, FUNC_U1TXD_BK);
288+
} else {
289+
PIN_PULLUP_DIS(PERIPHS_IO_MUX_U0TXD_U);
290+
PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0RXD_U, FUNC_U0RXD);
291+
PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD);
292+
}
293+
294+
UART_SetFlowCtrl(uart_no, pUARTConfig->flow_ctrl, pUARTConfig->UART_RxFlowThresh);
295+
UART_SetBaudrate(uart_no, pUARTConfig->baud_rate);
296+
297+
WRITE_PERI_REG(UART_CONF0(uart_no),
298+
((pUARTConfig->parity == USART_Parity_None) ? 0x0 : (UART_PARITY_EN | pUARTConfig->parity))
299+
| (pUARTConfig->stop_bits << UART_STOP_BIT_NUM_S)
300+
| (pUARTConfig->data_bits << UART_BIT_NUM_S)
301+
| ((pUARTConfig->flow_ctrl & USART_HardwareFlowControl_CTS) ? UART_TX_FLOW_EN : 0x0)
302+
| pUARTConfig->UART_InverseMask);
303+
304+
UART_ResetFifo(uart_no);
305+
}
306+
307+
void ICACHE_FLASH_ATTR
308+
UART_IntrConfig(UART_Port uart_no, UART_IntrConfTypeDef *pUARTIntrConf)
309+
{
310+
311+
uint32 reg_val = 0;
312+
UART_ClearIntrStatus(uart_no, UART_INTR_MASK);
313+
reg_val = READ_PERI_REG(UART_CONF1(uart_no)) & ~((UART_RX_FLOW_THRHD << UART_RX_FLOW_THRHD_S) | UART_RX_FLOW_EN) ;
314+
315+
reg_val |= ((pUARTIntrConf->UART_IntrEnMask & UART_RXFIFO_TOUT_INT_ENA) ?
316+
((((pUARTIntrConf->UART_RX_TimeOutIntrThresh)&UART_RX_TOUT_THRHD) << UART_RX_TOUT_THRHD_S) | UART_RX_TOUT_EN) : 0);
317+
318+
reg_val |= ((pUARTIntrConf->UART_IntrEnMask & UART_RXFIFO_FULL_INT_ENA) ?
319+
(((pUARTIntrConf->UART_RX_FifoFullIntrThresh)&UART_RXFIFO_FULL_THRHD) << UART_RXFIFO_FULL_THRHD_S) : 0);
320+
321+
reg_val |= ((pUARTIntrConf->UART_IntrEnMask & UART_TXFIFO_EMPTY_INT_ENA) ?
322+
(((pUARTIntrConf->UART_TX_FifoEmptyIntrThresh)&UART_TXFIFO_EMPTY_THRHD) << UART_TXFIFO_EMPTY_THRHD_S) : 0);
323+
324+
WRITE_PERI_REG(UART_CONF1(uart_no), reg_val);
325+
CLEAR_PERI_REG_MASK(UART_INT_ENA(uart_no), UART_INTR_MASK);
326+
SET_PERI_REG_MASK(UART_INT_ENA(uart_no), pUARTIntrConf->UART_IntrEnMask);
327+
}
328+
329+
LOCAL void
330+
uart0_rx_intr_handler(void *para)
331+
{
332+
/* uart0 and uart1 intr combine togther, when interrupt occur, see reg 0x3ff20020, bit2, bit0 represents
333+
* uart1 and uart0 respectively
334+
*/
335+
uint8 RcvChar;
336+
uint8 uart_no = UART0;//UartDev.buff_uart_no;
337+
uint8 fifo_len = 0;
338+
uint8 buf_idx = 0;
339+
uint8 fifo_tmp[128] = {0};
340+
341+
uint32 uart_intr_status = READ_PERI_REG(UART_INT_ST(uart_no)) ;
342+
343+
while (uart_intr_status != 0x0) {
344+
if (UART_FRM_ERR_INT_ST == (uart_intr_status & UART_FRM_ERR_INT_ST)) {
345+
//printf("FRM_ERR\r\n");
346+
WRITE_PERI_REG(UART_INT_CLR(uart_no), UART_FRM_ERR_INT_CLR);
347+
} else if (UART_RXFIFO_FULL_INT_ST == (uart_intr_status & UART_RXFIFO_FULL_INT_ST)) {
348+
printf("full\r\n");
349+
fifo_len = (READ_PERI_REG(UART_STATUS(UART0)) >> UART_RXFIFO_CNT_S)&UART_RXFIFO_CNT;
350+
buf_idx = 0;
351+
352+
while (buf_idx < fifo_len) {
353+
uart_tx_one_char(UART0, READ_PERI_REG(UART_FIFO(UART0)) & 0xFF);
354+
buf_idx++;
355+
}
356+
357+
WRITE_PERI_REG(UART_INT_CLR(UART0), UART_RXFIFO_FULL_INT_CLR);
358+
} else if (UART_RXFIFO_TOUT_INT_ST == (uart_intr_status & UART_RXFIFO_TOUT_INT_ST)) {
359+
printf("tout\r\n");
360+
fifo_len = (READ_PERI_REG(UART_STATUS(UART0)) >> UART_RXFIFO_CNT_S)&UART_RXFIFO_CNT;
361+
buf_idx = 0;
362+
363+
while (buf_idx < fifo_len) {
364+
uart_tx_one_char(UART0, READ_PERI_REG(UART_FIFO(UART0)) & 0xFF);
365+
buf_idx++;
366+
}
367+
368+
WRITE_PERI_REG(UART_INT_CLR(UART0), UART_RXFIFO_TOUT_INT_CLR);
369+
} else if (UART_TXFIFO_EMPTY_INT_ST == (uart_intr_status & UART_TXFIFO_EMPTY_INT_ST)) {
370+
printf("empty\n\r");
371+
WRITE_PERI_REG(UART_INT_CLR(uart_no), UART_TXFIFO_EMPTY_INT_CLR);
372+
CLEAR_PERI_REG_MASK(UART_INT_ENA(UART0), UART_TXFIFO_EMPTY_INT_ENA);
373+
} else {
374+
//skip
375+
}
376+
377+
uart_intr_status = READ_PERI_REG(UART_INT_ST(uart_no)) ;
378+
}
379+
}
166380

381+
void ICACHE_FLASH_ATTR
382+
uart_init_new(void)
383+
{
384+
UART_WaitTxFifoEmpty(UART0);
385+
UART_WaitTxFifoEmpty(UART1);
386+
387+
UART_ConfigTypeDef uart_config;
388+
uart_config.baud_rate = BIT_RATE_74880;
389+
uart_config.data_bits = UART_WordLength_8b;
390+
uart_config.parity = USART_Parity_None;
391+
uart_config.stop_bits = USART_StopBits_1;
392+
uart_config.flow_ctrl = USART_HardwareFlowControl_None;
393+
uart_config.UART_RxFlowThresh = 120;
394+
uart_config.UART_InverseMask = UART_None_Inverse;
395+
UART_ParamConfig(UART0, &uart_config);
396+
397+
UART_IntrConfTypeDef uart_intr;
398+
uart_intr.UART_IntrEnMask = UART_RXFIFO_TOUT_INT_ENA | UART_FRM_ERR_INT_ENA | UART_RXFIFO_FULL_INT_ENA | UART_TXFIFO_EMPTY_INT_ENA;
399+
uart_intr.UART_RX_FifoFullIntrThresh = 10;
400+
uart_intr.UART_RX_TimeOutIntrThresh = 2;
401+
uart_intr.UART_TX_FifoEmptyIntrThresh = 20;
402+
UART_IntrConfig(UART0, &uart_intr);
403+
404+
UART_SetPrintPort(UART0);
405+
UART_intr_handler_register(uart0_rx_intr_handler);
406+
ETS_UART_INTR_ENABLE();
407+
408+
/*
409+
UART_SetWordLength(UART0,UART_WordLength_8b);
410+
UART_SetStopBits(UART0,USART_StopBits_1);
411+
UART_SetParity(UART0,USART_Parity_None);
412+
UART_SetBaudrate(UART0,74880);
413+
UART_SetFlowCtrl(UART0,USART_HardwareFlowControl_None,0);
414+
*/
415+
416+
}

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