@llvm/pr-subscribers-backend-risc-v

Author: Jasmine Tang (badumbatish)

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index adbfbeb4669e7..d86ec003459d3 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -21477,6 +21477,14 @@ bool RISCVTargetLowering::canCreateUndefOrPoisonForTargetNode(
 
   // TODO: Add more target nodes.
   switch (Op.getOpcode()) {
+  case RISCVISD::SLLW:
+  case RISCVISD::SRAW:
+  case RISCVISD::SRLW:
+  case RISCVISD::RORW:
+  case RISCVISD::ROLW:
+    // Only the lower 5 bits of RHS are read, guaranteeing the rotate/shift
+    // amount is bounds.
+    return false;
   case RISCVISD::SELECT_CC:
     // Integer select_cc cannot create poison.
     // TODO: What are the FP poison semantics?

The only place where I see this piece of code used is via visitFreeze in llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp.

But in visiting freeze (hoping to hit sllw), freeze is still wrapping sext and shl, not sllw yet.

Therefore I'm not sure if there's any other tests to be constructed. I'm also not sure what kind of visible effects can I test for here? i.e even if freeze unwraps itself for a sllw inside, how does that change the assembly?

Putting it as draft for now

Test case is

define i64 @shl(i32 %x, i32 %y) {
; CHECK64I-LABEL: shl:
; CHECK64I:       # %bb.0:
; CHECK64I-NEXT:    sllw a0, a0, a1
; CHECK64I-NEXT:    ret
  %m = and i32 %y, 31
  %s = shl i32 %x, %m
  %r = sext i32 %s to i64
  %hhhh = freeze i64 %r
  ret i64 %r
}

@topperc Do you have any objections to this going in without tests?

@topperc Do you have any objections to this going in without tests?

No objection. Writing a test is probably tricky since this node appears after type legalization. So the freeze would also need to be created after type legalization to avoid it getting optimized earlier.