[RISCV] Unaligned vec mem => prefer alt opc vec #154153

mgudim · 2025-08-18T16:31:33Z

Return true in RISCVTTIImpl::preferAlternateOpcodeVectorization if
subtarget supports unaligned memory accesses.

llvmbot · 2025-08-18T16:32:14Z

@llvm/pr-subscribers-llvm-transforms

@llvm/pr-subscribers-backend-risc-v

Author: Mikhail Gudim (mgudim)

Changes

are supported.

Full diff: https://github.com/llvm/llvm-project/pull/154153.diff

2 Files Affected:

(modified) llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp (+4)
(modified) llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h (+1-1)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 85b3059d87da7..f49c3ae9bdea3 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2713,6 +2713,10 @@ unsigned RISCVTTIImpl::getMinTripCountTailFoldingThreshold() const {
   return RVVMinTripCount;
 }
 
+bool RISCVTTIImpl::preferAlternateOpcodeVectorization() const override {
+  return ST->enableUnalignedVectorMem();
+}
+
 TTI::AddressingModeKind
 RISCVTTIImpl::getPreferredAddressingMode(const Loop *L,
                                          ScalarEvolution *SE) const {
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index 6a1f4b3e3bedf..254908f97186c 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -132,7 +132,7 @@ class RISCVTTIImpl final : public BasicTTIImplBase<RISCVTTIImpl> {
 
   unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const override;
 
-  bool preferAlternateOpcodeVectorization() const override { return false; }
+  bool preferAlternateOpcodeVectorization() const override;
 
   bool preferEpilogueVectorization() const override {
     // Epilogue vectorization is usually unprofitable - tail folding or

alexey-bataev

Tests

topperc · 2025-08-18T18:22:45Z

vectorization is misspelled in title. Title is split into the description.

mgudim · 2025-08-18T20:03:45Z

Tests

@alexey-bataev I am actually struggling to come up with a simple test where split vectorization would trigger. Can you please point me to an example.

wangpc-pp · 2025-08-19T04:23:14Z

llvm/test/Transforms/SLPVectorizer/RISCV/alt-opc-vectorization.ll

+; UNALIGNED_VEC_MEM-NEXT:    store <8 x i8> [[TMP2]], ptr [[GEP_S0]], align 1
+; UNALIGNED_VEC_MEM-NEXT:    ret void
+;
+; NO_UNALIGNED_VEC_MEM-LABEL: define void @alternate_opcodes(


What is the difference? I may miss it…

No difference. I am trying to trigger the split vectorization path, but I can' t yet come up with simple IR to do that

mgudim · 2025-08-23T21:29:07Z

Tests

@alexey-bataev I am actually struggling to come up with a simple test where split vectorization would trigger. Can you please point me to an example.

ping

alexey-bataev · 2025-08-28T17:15:29Z

llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll

@@ -1,6 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
 ; RUN: opt -S -mtriple riscv64-unknown-linux-gnu < %s --passes=slp-vectorizer -mattr=+v | FileCheck %s
 ; RUN: opt -S -mtriple riscv64-unknown-linux-gnu < %s --passes=slp-vectorizer -mattr=+v -slp-threshold=-15 | FileCheck %s --check-prefix=THR15
+; RUN: opt -S -mtriple riscv64-unknown-linux-gnu < %s --passes=slp-vectorizer -mattr=+v,+unaligned-vector-mem | FileCheck %s --check-prefix=UNALIGNED_VEC_MEM


Does it affect TTI? Particularly, does it affect isLegalMaskedLoadStore? I do not see the difference in the results.
Need to teach TTI, that it is legal to have alignment less than the basic load type. I think you can try to do it for X86, I think it supports it.

Need to teach TTI, that it is legal to have alignment less than the basic load type

I think this is already present in isLegalMaskedLoadStore:

if (!ST->enableUnalignedVectorMem() && Alignment < ElemType.getStoreSize()) return false;

isLegalMaskedLoadStore returns true.

Could you check, please, if the test results are actually updated? Also, you can try to run test/Transforms/PhaseOrdering/AArch64/slpordering.ll, but try to run it for RISC-V and see, if it changes

Yes, sorry. It seems like I updated the test without building opt first.

Could you split this change and pre-commit the test at first?

Return `true` in `RISCVTTIImpl::preferAlternateOpcodeVectorization` if subtarget supports unaligned memory accesses.

mgudim · 2025-08-29T22:27:34Z

llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll

@@ -275,135 +275,414 @@ define i32 @test(ptr %pix1, ptr %pix2, i64 %idx.ext, i64 %idx.ext63, ptr %add.pt
 ; UNALIGNED_VEC_MEM-LABEL: define i32 @test(
 ; UNALIGNED_VEC_MEM-SAME: ptr [[PIX1:%.*]], ptr [[PIX2:%.*]], i64 [[IDX_EXT:%.*]], i64 [[IDX_EXT63:%.*]], ptr [[ADD_PTR:%.*]], ptr [[ADD_PTR64:%.*]]) #[[ATTR0:[0-9]+]] {
 ; UNALIGNED_VEC_MEM-NEXT:  entry:
+; UNALIGNED_VEC_MEM-NEXT:    [[TMP54:%.*]] = load i8, ptr [[PIX1]], align 1


So it seems like nothing gets vectorized now, is that what we should expect?

mgudim requested a review from alexey-bataev August 18, 2025 16:31

llvmbot added the backend:RISC-V label Aug 18, 2025

mgudim mentioned this pull request Aug 18, 2025

[SLPVectorizer] Widen strided loads. #153074

Open

alexey-bataev reviewed Aug 18, 2025

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mgudim force-pushed the prefer_alt_opc_vec branch from ae909f8 to 0f790de Compare August 18, 2025 16:49

mgudim force-pushed the prefer_alt_opc_vec branch from 0f790de to fdb931f Compare August 18, 2025 20:00

llvmbot added the llvm:transforms label Aug 18, 2025

mgudim changed the title ~~[RISCV] Prefer alt opcode vectorirazion if unaligned vector mem accesses~~ [RISCV] Unaligned vec mem => prefer alt opc vec Aug 18, 2025

wangpc-pp reviewed Aug 19, 2025

View reviewed changes

mgudim force-pushed the prefer_alt_opc_vec branch from fdb931f to 2f26eb4 Compare August 28, 2025 15:14

alexey-bataev reviewed Aug 28, 2025

View reviewed changes

Mikhail Gudim added 2 commits August 29, 2025 15:19

[RISCV] Unaligned vec mem => prefer alt opc vec

569f60b

Return `true` in `RISCVTTIImpl::preferAlternateOpcodeVectorization` if subtarget supports unaligned memory accesses.

updated checks in complex-loads.ll correctly.

efdd5b5

mgudim force-pushed the prefer_alt_opc_vec branch from cdcb2f5 to efdd5b5 Compare August 29, 2025 22:23

mgudim commented Aug 29, 2025

View reviewed changes

alexey-bataev approved these changes Aug 30, 2025

View reviewed changes

mgudim merged commit fe6b611 into llvm:main Aug 30, 2025
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[RISCV] Unaligned vec mem => prefer alt opc vec #154153

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[RISCV] Unaligned vec mem => prefer alt opc vec #154153

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