[DAGCombiner] add fold (xor (smin(x, C), C)) and fold (xor (smax(x, C), C)) #155141

rez5427 · 2025-08-24T05:42:18Z

Hi, I compared the following LLVM IR with GCC and Clang, and there is a small difference between the two. The LLVM IR is:

define i64 @test_smin_neg_one(i64 %a) {
  %1 = tail call i64 @llvm.smin.i64(i64 %a, i64 -1)
  %retval.0 = xor i64 %1, -1
  ret i64 %retval.0
}

GCC generates:

	cmp	x0, 0
	csinv	x0, xzr, x0, ge
	ret

Clang generates:

	cmn	x0, #1
	csinv	x8, x0, xzr, lt
	mvn	x0, x8
	ret

Clang keeps flipping x0 through x8 unnecessarily.
So I added the following folds to DAGCombiner:
fold (xor (smax(x, C), C)) -> select (x > C), xor(x, C), 0
fold (xor (smin(x, C), C)) -> select (x < C), xor(x, C), 0

alive2:
https://alive2.llvm.org/ce/z/NEeFyr

github-actions · 2025-08-24T05:42:35Z

Thank you for submitting a Pull Request (PR) to the LLVM Project!

This PR will be automatically labeled and the relevant teams will be notified.

If you wish to, you can add reviewers by using the "Reviewers" section on this page.

If this is not working for you, it is probably because you do not have write permissions for the repository. In which case you can instead tag reviewers by name in a comment by using @ followed by their GitHub username.

If you have received no comments on your PR for a week, you can request a review by "ping"ing the PR by adding a comment “Ping”. The common courtesy "ping" rate is once a week. Please remember that you are asking for valuable time from other developers.

If you have further questions, they may be answered by the LLVM GitHub User Guide.

You can also ask questions in a comment on this PR, on the LLVM Discord or on the forums.

llvmbot · 2025-08-24T05:43:05Z

@llvm/pr-subscribers-llvm-selectiondag

@llvm/pr-subscribers-backend-aarch64

Author: guan jian (rez5427)

Changes

Hi, I compared the following LLVM IR with GCC and Clang, and there is a small difference between the two. The LLVM IR is:

define i64 @<!-- -->test_smin_neg_one(i64 %a) {
  %1 = tail call i64 @<!-- -->llvm.smin.i64(i64 %a, i64 -1)
  %retval.0 = xor i64 %1, -1
  ret i64 %retval.0
}

GCC generates:

	cmp	x0, 0
	csinv	x0, xzr, x0, ge
	ret

Clang generates:

	cmn	x0, #<!-- -->1
	csinv	x8, x0, xzr, lt
	mvn	x0, x8
	ret

Clang keeps flipping x0 through x8 unnecessarily.
So I added the following folds to DAGCombiner:
fold (xor (smax(x, C), C)) -> select (x > C), xor(x, C), 0
fold (xor (smin(x, C), C)) -> select (x < C), xor(x, C), 0

Full diff: https://github.com/llvm/llvm-project/pull/155141.diff

2 Files Affected:

(modified) llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (+42)
(added) llvm/test/CodeGen/AArch64/xor-smin-smax.ll (+75)

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index cee593def653c..681da941c5225 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -10086,6 +10086,48 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
   if (SDValue Combined = combineCarryDiamond(DAG, TLI, N0, N1, N))
     return Combined;
 
+  // fold (xor (smin(x, C), C)) -> select (x < C), xor(x, C), 0
+  // fold (xor (smin(C, x), C)) -> select (x < C), xor(x, C), 0
+  if (N0.getOpcode() == ISD::SMIN && N0.hasOneUse()) {
+    SDValue Op0 = N0.getOperand(0);
+    SDValue Op1 = N0.getOperand(1);
+
+    if(Op1 != N1) {
+      std::swap(Op0, Op1);
+    }
+
+    if (Op1 == N1) {
+      if (isa<ConstantSDNode>(N1)) {
+          EVT CCVT = getSetCCResultType(VT);
+          SDValue Cmp = DAG.getSetCC(SDLoc(N), CCVT, Op0, N1, ISD::SETLT);
+          SDValue XorXC = DAG.getNode(ISD::XOR, SDLoc(N), VT, Op0, N1);
+          SDValue Zero = DAG.getConstant(0, SDLoc(N), VT);
+          return DAG.getSelect(SDLoc(N), VT, Cmp, XorXC, Zero);
+      }
+    }
+  }
+
+  // fold (xor (smax(x, C), C)) -> select (x > C), xor(x, C), 0
+  // fold (xor (smax(C, x), C)) -> select (x > C), xor(x, C), 0
+  if (N0.getOpcode() == ISD::SMAX && N0.hasOneUse()) {
+    SDValue Op0 = N0.getOperand(0);
+    SDValue Op1 = N0.getOperand(1);
+
+    if(Op1 != N1) {
+      std::swap(Op0, Op1);
+    }
+
+    if (Op1 == N1) {
+      if (isa<ConstantSDNode>(N1)) {
+        EVT CCVT = getSetCCResultType(VT);
+        SDValue Cmp = DAG.getSetCC(SDLoc(N), CCVT, Op0, N1, ISD::SETGT);
+        SDValue XorXC = DAG.getNode(ISD::XOR, SDLoc(N), VT, Op0, N1);
+        SDValue Zero = DAG.getConstant(0, SDLoc(N), VT);
+        return DAG.getSelect(SDLoc(N), VT, Cmp, XorXC, Zero);
+      }
+    }
+  }
+
   return SDValue();
 }
 
diff --git a/llvm/test/CodeGen/AArch64/xor-smin-smax.ll b/llvm/test/CodeGen/AArch64/xor-smin-smax.ll
new file mode 100644
index 0000000000000..cfdec2da61c7a
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/xor-smin-smax.ll
@@ -0,0 +1,75 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
+
+; Test for DAGCombiner optimization: fold (xor (smin(x, C), C)) -> select (x < C), xor (x, C), 0
+
+define i64 @test_smin_neg_one(i64 %a) {
+; CHECK-LABEL: test_smin_neg_one:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    cmn x0, #1
+; CHECK-NEXT:    csinv x0, xzr, x0, ge
+; CHECK-NEXT:    ret
+  %1 = tail call i64 @llvm.smin.i64(i64 %a, i64 -1)
+  %retval.0 = xor i64 %1, -1
+  ret i64 %retval.0
+}
+
+define i64 @test_smin_zero(i64 %a) {
+; CHECK-LABEL: test_smin_zero:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and x0, x0, x0, asr #63
+; CHECK-NEXT:    ret
+  %1 = tail call i64 @llvm.smin.i64(i64 %a, i64 0)
+  %retval.0 = xor i64 %1, 0
+  ret i64 %retval.0
+}
+
+define i64 @test_smin_constant(i64 %a) {
+; CHECK-LABEL: test_smin_constant:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    eor x8, x0, #0x8
+; CHECK-NEXT:    cmp x0, #8
+; CHECK-NEXT:    csel x0, x8, xzr, lt
+; CHECK-NEXT:    ret
+  %1 = tail call i64 @llvm.smin.i64(i64 %a, i64 8)
+  %retval.0 = xor i64 %1, 8
+  ret i64 %retval.0
+}
+
+; Test for DAGCombiner optimization: fold (xor (smax(x, C), C)) -> select (x > C), xor (x, C), 0
+
+define i64 @test_smax_neg_one(i64 %a) {
+; CHECK-LABEL: test_smax_neg_one:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mvn x8, x0
+; CHECK-NEXT:    bic x0, x8, x0, asr #63
+; CHECK-NEXT:    ret
+  %1 = tail call i64 @llvm.smax.i64(i64 %a, i64 -1)
+  %retval.0 = xor i64 %1, -1
+  ret i64 %retval.0
+}
+
+define i64 @test_smax_zero(i64 %a) {
+; CHECK-LABEL: test_smax_zero:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    bic x0, x0, x0, asr #63
+; CHECK-NEXT:    ret
+  %1 = tail call i64 @llvm.smax.i64(i64 %a, i64 0)
+  %retval.0 = xor i64 %1, 0
+  ret i64 %retval.0
+}
+
+define i64 @test_smax_constant(i64 %a) {
+; CHECK-LABEL: test_smax_constant:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    eor x8, x0, #0x8
+; CHECK-NEXT:    cmp x0, #8
+; CHECK-NEXT:    csel x0, x8, xzr, gt
+; CHECK-NEXT:    ret
+  %1 = tail call i64 @llvm.smax.i64(i64 %a, i64 8)
+  %retval.0 = xor i64 %1, 8
+  ret i64 %retval.0
+}
+
+declare i64 @llvm.smin.i64(i64, i64)
+declare i64 @llvm.smax.i64(i64, i64)
\ No newline at end of file

github-actions · 2025-08-24T07:17:24Z

✅ With the latest revision this PR passed the C/C++ code formatter.

…, C), 0

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

RKSimon

Should we avoid the fold if the minmax op is legal? xor+minmax is likely to be lighter than xor+cmp+select

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

llvm/test/CodeGen/AArch64/xor-smin-smax.ll

Co-authored-by: Matt Arsenault <arsenm2@gmail.com>

RKSimon · 2025-08-28T11:25:30Z

Please can you add alive2 test links to the summary?

rez5427 · 2025-08-29T07:24:53Z

Please can you add alive2 test links to the summary?

https://alive2.llvm.org/ce/z/NEeFyr

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

rez5427 · 2025-09-02T17:36:54Z

ping

RKSimon

One last minor

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

llvmbot added backend:AArch64 llvm:SelectionDAG SelectionDAGISel as well labels Aug 24, 2025

davemgreen requested review from RKSimon, davemgreen and topperc August 24, 2025 07:16

[DAGCombiner] add fold (xor (smin(x, C), C)) -> select (x < C), xor(x…

f8575c9

…, C), 0

rez5427 force-pushed the fold-xor-min-constant branch from 9e126e2 to f8575c9 Compare August 24, 2025 07:50

RKSimon reviewed Aug 24, 2025

View reviewed changes

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Show resolved Hide resolved

davemgreen reviewed Aug 24, 2025

View reviewed changes

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Outdated Show resolved Hide resolved

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Show resolved Hide resolved

arsenm reviewed Aug 25, 2025

View reviewed changes

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Show resolved Hide resolved

rez5427 force-pushed the fold-xor-min-constant branch from be85e72 to c1f5bb1 Compare August 25, 2025 17:06

Combining umax umin, smin, smax

c784fd8

rez5427 force-pushed the fold-xor-min-constant branch from c1f5bb1 to c784fd8 Compare August 25, 2025 17:10

Use sd_match

76c16c7

RKSimon reviewed Aug 27, 2025

View reviewed changes

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Show resolved Hide resolved

RKSimon reviewed Aug 27, 2025

View reviewed changes

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Show resolved Hide resolved

Use m_specific and DL

5723e18

arsenm reviewed Aug 27, 2025

View reviewed changes

llvm/test/CodeGen/AArch64/xor-smin-smax.ll Outdated Show resolved Hide resolved

Update llvm/test/CodeGen/AArch64/xor-smin-smax.ll

7e81126

Co-authored-by: Matt Arsenault <arsenm2@gmail.com>

rez5427 requested review from davemgreen, RKSimon and arsenm August 29, 2025 07:59

RKSimon reviewed Aug 29, 2025

View reviewed changes

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Show resolved Hide resolved

Use freeze N1

d6359db

rez5427 requested a review from RKSimon September 4, 2025 08:00

RKSimon reviewed Sep 4, 2025

View reviewed changes

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Show resolved Hide resolved

remove redundent bracket

d22128e

rez5427 force-pushed the fold-xor-min-constant branch from 7cf22b3 to d22128e Compare September 4, 2025 13:28

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

Uh oh!

[DAGCombiner] add fold (xor (smin(x, C), C)) and fold (xor (smax(x, C), C)) #155141

[DAGCombiner] add fold (xor (smin(x, C), C)) and fold (xor (smax(x, C), C)) #155141

rez5427 commented Aug 24, 2025 •

edited

Loading

Uh oh!

github-actions bot commented Aug 24, 2025

Uh oh!

llvmbot commented Aug 24, 2025 •

edited

Loading

Uh oh!

github-actions bot commented Aug 24, 2025 •

edited

Loading

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

RKSimon left a comment

Uh oh!

Uh oh!

Uh oh!

Uh oh!

RKSimon commented Aug 28, 2025

Uh oh!

rez5427 commented Aug 29, 2025

Uh oh!

Uh oh!

rez5427 commented Sep 2, 2025

Uh oh!

RKSimon left a comment

Uh oh!

Uh oh!

Uh oh!

[DAGCombiner] add fold (xor (smin(x, C), C)) and fold (xor (smax(x, C), C)) #155141

Are you sure you want to change the base?

[DAGCombiner] add fold (xor (smin(x, C), C)) and fold (xor (smax(x, C), C)) #155141

Conversation

rez5427 commented Aug 24, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

github-actions bot commented Aug 24, 2025

Uh oh!

llvmbot commented Aug 24, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

github-actions bot commented Aug 24, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

RKSimon left a comment

Choose a reason for hiding this comment

Uh oh!

Uh oh!

Uh oh!

Uh oh!

RKSimon commented Aug 28, 2025

Uh oh!

rez5427 commented Aug 29, 2025

Uh oh!

Uh oh!

rez5427 commented Sep 2, 2025

Uh oh!

RKSimon left a comment

Choose a reason for hiding this comment

Uh oh!

Uh oh!

Uh oh!

rez5427 commented Aug 24, 2025 •

edited

Loading

llvmbot commented Aug 24, 2025 •

edited

Loading

github-actions bot commented Aug 24, 2025 •

edited

Loading