@llvm/pr-subscribers-backend-amdgpu

Author: Patrick Simmons (linuxrocks123)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
index dbe74b1b08f8c..8c514714bd7dd 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
@@ -2391,6 +2391,16 @@ bool SchedGroup::canAddMI(const MachineInstr &MI) const {
   if (MI.isMetaInstruction())
     Result = false;
 
+  else if (MI.isInlineAsm()) {
+    std::string Text = MI.getOperand(0).getSymbolName();
+    if (Text.find("SGMASK:") != std::string::npos) {
+      Text = Text.substr(Text.find("SGMASK:") + strlen("SGMASK:"));
+      Text = Text.substr(0, Text.find_first_of(" \t\r\n"));
+      unsigned long InlineAsmMask = std::stoul(Text, nullptr, 0);
+      Result = ((unsigned long)SGMask & InlineAsmMask) != 0;
+    }
+  }
+
   else if (((SGMask & SchedGroupMask::ALU) != SchedGroupMask::NONE) &&
            (TII->isVALU(MI) || TII->isMFMAorWMMA(MI) || TII->isSALU(MI) ||
             TII->isTRANS(MI)))

This PR allows the user to specify sched group barrier information for inline asm instructions. The mechanism for doing so is adding a comment with the text "SGMASK:" inside the inline asm string. The contents of "" should be the schedule barrier groups you want to group the inline asm with. So, for example, if your inline asm is a VALU instruction, you would have an inline asm statement that looks like this:

asm ("v_add_f32_e32 %[result], %[lhs], %[rhs] ; SGMASK:0x2"
             : [result] "=v"(result)
             : [lhs] "v"(lhs), [rhs] "v"(rhs));

Because of the "SGMASK:0x2", sched group barrier instructions will now be able to recognize that the inline asm instruction is a VALU instruction and schedule it accordingly.

@arsenm Thanks, I switched to using StringRef.

Regarding the parsing of the inline assembly, the goal of this PR is to allow the user to optionally specify the schedule group mask for a specific inline assembly instruction to allow schedule group barriers to work correctly with that instruction. Parsing a special token out of the inline assembly is the only reasonable mechanism I currently see for accomplishing that, but I am open to suggestions.

@arsenm Thanks, I switched to using StringRef.

Regarding the parsing of the inline assembly, the goal of this PR is to allow the user to optionally specify the schedule group mask for a specific inline assembly instruction to allow schedule group barriers to work correctly with that instruction. Parsing a special token out of the inline assembly is the only reasonable mechanism I currently see for accomplishing that, but I am open to suggestions.

I am going to outright reject the concept of trying to parse the content of inline assembly. I am firmly in the camp of wont fixing any performance issue involving inline assembly

#157080 also proposes codifying not doing things like this