diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index ea74d6a2071d9..147b710d6df43 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -10539,16 +10539,8 @@ SDValue ARMTargetLowering::LowerCMP(SDValue Op, SelectionDAG &DAG) const {
   }
 
   // Generate the operation with flags
-  SDValue OpWithFlags;
-  if (Opcode == ARMISD::ADDC) {
-    // Use ADDC: LHS + RHS (where RHS was 0 - X, now X)
-    OpWithFlags = DAG.getNode(ARMISD::ADDC, dl,
-                              DAG.getVTList(MVT::i32, FlagsVT), LHS, RHS);
-  } else {
-    // Use ARMISD::SUBC to generate SUBS instruction (subtract with flags)
-    OpWithFlags = DAG.getNode(ARMISD::SUBC, dl,
-                              DAG.getVTList(MVT::i32, FlagsVT), LHS, RHS);
-  }
+  SDValue OpWithFlags = DAG.getNode(Opcode, dl,
+                                    DAG.getVTList(MVT::i32, FlagsVT), LHS, RHS);
 
   SDValue OpResult = OpWithFlags.getValue(0); // The operation result
   SDValue Flags = OpWithFlags.getValue(1);    // The flags