AMDGPU: Reorder arguments of DS_Real_gfx12 (NFC) #156405
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The DS multiclasses are poorly named. The base forms include the legacy pseudo with the m0 implicit use, plus a _gfx9 suffixed version without. The _gfx9 multiclass only defines an unsuffixed version without m0, so use tha one. Fixes unnecessarily depending on m0 for ds_cond_sub_rtn_u32.
This was using the legacy multiclass which assumes the base form has an m0 use. Use the versions which assume no m0 as the base name. Most of the diff is shuffling around the pattern classes to avoid trying to match the nonexistent m0-having form.
This helps shrink the diff in a future change.
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@llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) ChangesThis helps shrink the diff in a future change. Full diff: https://github.com/llvm/llvm-project/pull/156405.diff 1 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td
index 2de89e1262e9c..a9376250931b6 100644
--- a/llvm/lib/Target/AMDGPU/DSInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -1360,8 +1360,10 @@ class Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12<bits<8> op, DS_Pseudo ps, int ef,
// GFX12.
//===----------------------------------------------------------------------===//
-multiclass DS_Real_gfx12<bits<8> op, string name = !tolower(NAME)> {
- defvar ps = !cast<DS_Pseudo>(NAME);
+multiclass DS_Real_gfx12<bits<8> op,
+ DS_Pseudo ps = !cast<DS_Pseudo>(NAME),
+ string name = !tolower(NAME)> {
+
let AssemblerPredicate = isGFX12Plus in {
let DecoderNamespace = "GFX12" in
def _gfx12 :
@@ -1372,14 +1374,20 @@ multiclass DS_Real_gfx12<bits<8> op, string name = !tolower(NAME)> {
} // End AssemblerPredicate
}
-defm DS_MIN_F32 : DS_Real_gfx12<0x012, "ds_min_num_f32">;
-defm DS_MAX_F32 : DS_Real_gfx12<0x013, "ds_max_num_f32">;
-defm DS_MIN_RTN_F32 : DS_Real_gfx12<0x032, "ds_min_num_rtn_f32">;
-defm DS_MAX_RTN_F32 : DS_Real_gfx12<0x033, "ds_max_num_rtn_f32">;
-defm DS_MIN_F64 : DS_Real_gfx12<0x052, "ds_min_num_f64">;
-defm DS_MAX_F64 : DS_Real_gfx12<0x053, "ds_max_num_f64">;
-defm DS_MIN_RTN_F64 : DS_Real_gfx12<0x072, "ds_min_num_rtn_f64">;
-defm DS_MAX_RTN_F64 : DS_Real_gfx12<0x073, "ds_max_num_rtn_f64">;
+// Helper to avoid repeating the pseudo-name if we only need to set
+// the gfx12 name.
+multiclass DS_Real_gfx12_with_name<bits<8> op, string name> {
+ defm "" : DS_Real_gfx12<op, !cast<DS_Pseudo>(NAME), name>;
+}
+
+defm DS_MIN_F32 : DS_Real_gfx12_with_name<0x012, "ds_min_num_f32">;
+defm DS_MAX_F32 : DS_Real_gfx12_with_name<0x013, "ds_max_num_f32">;
+defm DS_MIN_RTN_F32 : DS_Real_gfx12_with_name<0x032, "ds_min_num_rtn_f32">;
+defm DS_MAX_RTN_F32 : DS_Real_gfx12_with_name<0x033, "ds_max_num_rtn_f32">;
+defm DS_MIN_F64 : DS_Real_gfx12_with_name<0x052, "ds_min_num_f64">;
+defm DS_MAX_F64 : DS_Real_gfx12_with_name<0x053, "ds_max_num_f64">;
+defm DS_MIN_RTN_F64 : DS_Real_gfx12_with_name<0x072, "ds_min_num_rtn_f64">;
+defm DS_MAX_RTN_F64 : DS_Real_gfx12_with_name<0x073, "ds_max_num_rtn_f64">;
defm DS_COND_SUB_U32 : DS_Real_gfx12<0x098>;
defm DS_SUB_CLAMP_U32 : DS_Real_gfx12<0x099>;
defm DS_COND_SUB_RTN_U32 : DS_Real_gfx12<0x0a8>;
@@ -1395,7 +1403,7 @@ defm DS_LOAD_TR6_B96 : DS_Real_gfx12<0x0fb>;
defm DS_LOAD_TR16_B128 : DS_Real_gfx12<0x0fc>;
defm DS_LOAD_TR8_B64 : DS_Real_gfx12<0x0fd>;
-defm DS_BVH_STACK_RTN_B32 : DS_Real_gfx12<0x0e0,
+defm DS_BVH_STACK_RTN_B32 : DS_Real_gfx12_with_name<0x0e0,
"ds_bvh_stack_push4_pop1_rtn_b32">;
defm DS_BVH_STACK_PUSH8_POP1_RTN_B32 : DS_Real_gfx12<0x0e1>;
defm DS_BVH_STACK_PUSH8_POP2_RTN_B64 : DS_Real_gfx12<0x0e2>;
@@ -1424,8 +1432,8 @@ def : MnemonicAlias<"ds_load_tr_b128", "ds_load_tr16_b128">, Requires<[isGFX1250
// GFX11.
//===----------------------------------------------------------------------===//
-multiclass DS_Real_gfx11<bits<8> op, string name = !tolower(NAME)> {
- defvar ps = !cast<DS_Pseudo>(NAME);
+multiclass DS_Real_gfx11<bits<8> op, DS_Pseudo ps = !cast<DS_Pseudo>(NAME),
+ string name = !tolower(NAME)> {
let AssemblerPredicate = isGFX11Only in {
let DecoderNamespace = "GFX11" in
def _gfx11 :
@@ -1436,8 +1444,11 @@ multiclass DS_Real_gfx11<bits<8> op, string name = !tolower(NAME)> {
} // End AssemblerPredicate
}
-multiclass DS_Real_gfx11_gfx12<bits<8> op, string name = !tolower(NAME)>
- : DS_Real_gfx11<op, name>, DS_Real_gfx12<op, name>;
+multiclass DS_Real_gfx11_gfx12<bits<8> op,
+ string name = !tolower(NAME),
+ DS_Pseudo ps = !cast<DS_Pseudo>(NAME)>
+ : DS_Real_gfx11<op, ps, name>,
+ DS_Real_gfx12<op, ps, name>;
defm DS_WRITE_B32 : DS_Real_gfx11_gfx12<0x00d, "ds_store_b32">;
defm DS_WRITE2_B32 : DS_Real_gfx11_gfx12<0x00e, "ds_store_2addr_b32">;
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This was referenced Sep 2, 2025
rampitec
approved these changes
Sep 2, 2025
Base automatically changed from
users/arsenm/amdgpu/fix/gfx94-ds-atomics-using-m0
to
main
September 2, 2025 23:58
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This helps shrink the diff in a future change.