AMDGPU: Remove dead code for printing DFP immediates #156644
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Nothing in the backend uses these, so there's no reason to support printing them.
frederik-h
requested changes
Sep 3, 2025
frederik-h
approved these changes
Sep 3, 2025
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@llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) ChangesNothing in the backend uses these, so there's no reason Full diff: https://github.com/llvm/llvm-project/pull/156644.diff 1 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index b9cbf35fcbec6..af6b7a9e7fdeb 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -792,22 +792,6 @@ void AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo,
// custom printer.
llvm_unreachable("unexpected immediate operand type");
}
- } else if (Op.isDFPImm()) {
- double Value = bit_cast<double>(Op.getDFPImm());
- // We special case 0.0 because otherwise it will be printed as an integer.
- if (Value == 0.0)
- O << "0.0";
- else {
- const MCInstrDesc &Desc = MII.get(MI->getOpcode());
- int RCID = Desc.operands()[OpNo].RegClass;
- unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID));
- if (RCBits == 32)
- printImmediate32(llvm::bit_cast<uint32_t>((float)Value), STI, O);
- else if (RCBits == 64)
- printImmediate64(llvm::bit_cast<uint64_t>(Value), STI, O, true);
- else
- llvm_unreachable("Invalid register class size");
- }
} else if (Op.isExpr()) {
const MCExpr *Exp = Op.getExpr();
MAI.printExpr(O, *Exp);
@@ -890,7 +874,7 @@ void AMDGPUInstPrinter::printOperandAndFPInputMods(const MCInst *MI,
if (OpNo + 1 < MI->getNumOperands() &&
(InputModifiers & SISrcMods::ABS) == 0) {
const MCOperand &Op = MI->getOperand(OpNo + 1);
- NegMnemo = Op.isImm() || Op.isDFPImm();
+ NegMnemo = Op.isImm();
}
if (NegMnemo) {
O << "neg(";
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Nothing in the backend uses these, so there's no reason
to support printing them.