AMDGPU: Remove the DS special case in getRegClass #156696
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@llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) ChangesThese instructions should now have proper representation Full diff: https://github.com/llvm/llvm-project/pull/156696.diff 1 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 2b187c641da1c..981d31bc9b572 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -5960,7 +5960,7 @@ adjustAllocatableRegClass(const GCNSubtarget &ST, const SIRegisterInfo &RI,
if ((IsAllocatable || !ST.hasGFX90AInsts()) &&
(((TID.mayLoad() || TID.mayStore()) &&
!(TID.TSFlags & SIInstrFlags::Spill)) ||
- (TID.TSFlags & (SIInstrFlags::DS | SIInstrFlags::MIMG)))) {
+ (TID.TSFlags & SIInstrFlags::MIMG))) {
switch (RCID) {
case AMDGPU::AV_32RegClassID:
RCID = AMDGPU::VGPR_32RegClassID;
@@ -5996,24 +5996,20 @@ const TargetRegisterClass *SIInstrInfo::getRegClass(const MCInstrDesc &TID,
return nullptr;
auto RegClass = TID.operands()[OpNum].RegClass;
bool IsAllocatable = false;
- if (TID.TSFlags & (SIInstrFlags::DS | SIInstrFlags::FLAT)) {
+ if (TID.TSFlags & SIInstrFlags::FLAT) {
// vdst and vdata should be both VGPR or AGPR, same for the DS instructions
// with two data operands. Request register class constrained to VGPR only
// of both operands present as Machine Copy Propagation can not check this
// constraint and possibly other passes too.
//
- // The check is limited to FLAT and DS because atomics in non-flat encoding
- // have their vdst and vdata tied to be the same register.
- const int VDstIdx = AMDGPU::getNamedOperandIdx(TID.Opcode,
- AMDGPU::OpName::vdst);
- const int DataIdx = AMDGPU::getNamedOperandIdx(TID.Opcode,
- (TID.TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0
- : AMDGPU::OpName::vdata);
- if (DataIdx != -1) {
- IsAllocatable = VDstIdx != -1 || AMDGPU::hasNamedOperand(
- TID.Opcode, AMDGPU::OpName::data1);
- }
+ // The check is limited to FLAT because atomics in non-flat encoding have
+ // their vdst and vdata tied to be the same register, and DS instructions
+ // have separate instruction definitions with AGPR and VGPR operand lists.
+ IsAllocatable =
+ AMDGPU::hasNamedOperand(TID.Opcode, AMDGPU::OpName::vdata) &&
+ AMDGPU::hasNamedOperand(TID.Opcode, AMDGPU::OpName::vdst);
}
+
return adjustAllocatableRegClass(ST, RI, TID, RegClass, IsAllocatable);
}
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rampitec
approved these changes
Sep 3, 2025
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These are 2-data operations that need to use all-AGPR or all-VGPR inputs. Stop defining them with AVLdSt data operands, and add _agpr variants.
Correctly model these without AV_* operands. This is another step towards removing the special casing in TargetInstrInfo::getRegClass. Also add some tests for this.
These instructions should now have proper representation with separate instructions for operands which must be paired.
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Base automatically changed from
users/arsenm/amdgpu/add-agpr-ds-permute-insts
to
main
September 4, 2025 06:14
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These instructions should now have proper representation
with separate instructions for operands which must be paired.