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[ARM][TargetLowering] Combine Level should not be a factor in shouldFoldConstantShiftPairToMask (NFC) #156949

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[ARM][TargetLowering] Combine Level should not be a factor in shouldFoldConstantShiftPairToMask (NFC) #156949

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3 changes: 1 addition & 2 deletions llvm/include/llvm/CodeGen/TargetLowering.h
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Expand Up @@ -854,8 +854,7 @@ class LLVM_ABI TargetLoweringBase {
/// This is usually true on most targets. But some targets, like Thumb1,
/// have immediate shift instructions, but no immediate "and" instruction;
/// this makes the fold unprofitable.
virtual bool shouldFoldConstantShiftPairToMask(const SDNode *N,
CombineLevel Level) const {
virtual bool shouldFoldConstantShiftPairToMask(const SDNode *N) const {
return true;
}

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4 changes: 2 additions & 2 deletions llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Expand Up @@ -10521,7 +10521,7 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
// folding this will increase the total number of instructions.
if (N0.getOpcode() == ISD::SRL &&
(N0.getOperand(1) == N1 || N0.hasOneUse()) &&
TLI.shouldFoldConstantShiftPairToMask(N, Level)) {
TLI.shouldFoldConstantShiftPairToMask(N)) {
if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), MatchShiftAmount,
/*AllowUndefs*/ false,
/*AllowTypeMismatch*/ true)) {
Expand Down Expand Up @@ -11100,7 +11100,7 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
// fold (srl (shl x, c1), c2) -> (and (shl x, (sub c1, c2), MASK) or
// (and (srl x, (sub c2, c1), MASK)
if ((N0.getOperand(1) == N1 || N0->hasOneUse()) &&
TLI.shouldFoldConstantShiftPairToMask(N, Level)) {
TLI.shouldFoldConstantShiftPairToMask(N)) {
auto MatchShiftAmount = [OpSizeInBits](ConstantSDNode *LHS,
ConstantSDNode *RHS) {
const APInt &LHSC = LHS->getAPIntValue();
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Expand Up @@ -18280,7 +18280,7 @@ bool AArch64TargetLowering::isDesirableToCommuteXorWithShift(
}

bool AArch64TargetLowering::shouldFoldConstantShiftPairToMask(
const SDNode *N, CombineLevel Level) const {
const SDNode *N) const {
assert(((N->getOpcode() == ISD::SHL &&
N->getOperand(0).getOpcode() == ISD::SRL) ||
(N->getOpcode() == ISD::SRL &&
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3 changes: 1 addition & 2 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.h
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Expand Up @@ -297,8 +297,7 @@ class AArch64TargetLowering : public TargetLowering {
bool isDesirableToCommuteXorWithShift(const SDNode *N) const override;

/// Return true if it is profitable to fold a pair of shifts into a mask.
bool shouldFoldConstantShiftPairToMask(const SDNode *N,
CombineLevel Level) const override;
bool shouldFoldConstantShiftPairToMask(const SDNode *N) const override;

bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, EVT VT,
unsigned SelectOpcode, SDValue X,
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5 changes: 3 additions & 2 deletions llvm/lib/Target/ARM/ARMISelLowering.cpp
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Expand Up @@ -13878,7 +13878,7 @@ bool ARMTargetLowering::isDesirableToCommuteXorWithShift(
}

bool ARMTargetLowering::shouldFoldConstantShiftPairToMask(
const SDNode *N, CombineLevel Level) const {
const SDNode *N) const {
assert(((N->getOpcode() == ISD::SHL &&
N->getOperand(0).getOpcode() == ISD::SRL) ||
(N->getOpcode() == ISD::SRL &&
Expand All @@ -13888,7 +13888,8 @@ bool ARMTargetLowering::shouldFoldConstantShiftPairToMask(
if (!Subtarget->isThumb1Only())
return true;

if (Level == BeforeLegalizeTypes)
EVT VT = N->getValueType(0);
if (VT.getScalarSizeInBits() > 32)
return true;

return false;
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3 changes: 1 addition & 2 deletions llvm/lib/Target/ARM/ARMISelLowering.h
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Expand Up @@ -770,8 +770,7 @@ class VectorType;

bool isDesirableToCommuteXorWithShift(const SDNode *N) const override;

bool shouldFoldConstantShiftPairToMask(const SDNode *N,
CombineLevel Level) const override;
bool shouldFoldConstantShiftPairToMask(const SDNode *N) const override;

bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, EVT VT,
unsigned SelectOpcode, SDValue X,
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/Mips/MipsISelLowering.cpp
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Expand Up @@ -1306,7 +1306,7 @@ bool MipsTargetLowering::hasBitTest(SDValue X, SDValue Y) const {
}

bool MipsTargetLowering::shouldFoldConstantShiftPairToMask(
const SDNode *N, CombineLevel Level) const {
const SDNode *N) const {
assert(((N->getOpcode() == ISD::SHL &&
N->getOperand(0).getOpcode() == ISD::SRL) ||
(N->getOpcode() == ISD::SRL &&
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3 changes: 1 addition & 2 deletions llvm/lib/Target/Mips/MipsISelLowering.h
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Expand Up @@ -290,8 +290,7 @@ class TargetRegisterClass;
bool isCheapToSpeculateCttz(Type *Ty) const override;
bool isCheapToSpeculateCtlz(Type *Ty) const override;
bool hasBitTest(SDValue X, SDValue Y) const override;
bool shouldFoldConstantShiftPairToMask(const SDNode *N,
CombineLevel Level) const override;
bool shouldFoldConstantShiftPairToMask(const SDNode *N) const override;

/// Return the register type for a given MVT, ensuring vectors are treated
/// as a series of gpr sized integers.
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4 changes: 2 additions & 2 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
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Expand Up @@ -3638,7 +3638,7 @@ bool X86TargetLowering::preferScalarizeSplat(SDNode *N) const {
}

bool X86TargetLowering::shouldFoldConstantShiftPairToMask(
const SDNode *N, CombineLevel Level) const {
const SDNode *N) const {
assert(((N->getOpcode() == ISD::SHL &&
N->getOperand(0).getOpcode() == ISD::SRL) ||
(N->getOpcode() == ISD::SRL &&
Expand All @@ -3653,7 +3653,7 @@ bool X86TargetLowering::shouldFoldConstantShiftPairToMask(
// the fold for non-splats yet.
return N->getOperand(1) == N->getOperand(0).getOperand(1);
}
return TargetLoweringBase::shouldFoldConstantShiftPairToMask(N, Level);
return TargetLoweringBase::shouldFoldConstantShiftPairToMask(N);
}

bool X86TargetLowering::shouldFoldMaskToVariableShiftPair(SDValue Y) const {
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3 changes: 1 addition & 2 deletions llvm/lib/Target/X86/X86ISelLowering.h
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Expand Up @@ -1240,8 +1240,7 @@ namespace llvm {
getJumpConditionMergingParams(Instruction::BinaryOps Opc, const Value *Lhs,
const Value *Rhs) const override;

bool shouldFoldConstantShiftPairToMask(const SDNode *N,
CombineLevel Level) const override;
bool shouldFoldConstantShiftPairToMask(const SDNode *N) const override;

bool shouldFoldMaskToVariableShiftPair(SDValue Y) const override;

Expand Down