[RISCV] Add th.ext(u) to RISCVDAGToDAGISel::hasAllNBitUsers. #157133
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The instructions are being used by the scalar efficiency SIG to determine if we should have a standard instruction. Improving our support for these instructions may give better data for their analysis. I'll follow up by adding this to RISCVOptWInstrs too which will remove the 'w' suffixes added here.
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@llvm/pr-subscribers-backend-risc-v Author: Craig Topper (topperc) ChangesThese instructions are being used by the scalar efficiency SIG to determine if we should have a standard instruction. Improving our support for these instructions may give better data for their analysis. I'll follow up by adding this to RISCVOptWInstrs too which will remove the 'w' suffixes added here. Full diff: https://github.com/llvm/llvm-project/pull/157133.diff 3 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 142414ddf7132..e84bf0eab08d7 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -3937,6 +3937,15 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits,
if (Use.getOperandNo() == 0 && Bits >= 32)
break;
return false;
+ case RISCV::TH_EXT:
+ case RISCV::TH_EXTU: {
+ unsigned Msb = User->getConstantOperandVal(1);
+ unsigned Lsb = User->getConstantOperandVal(2);
+ // Behavior of Msb < Lsb is not well documented.
+ if (Msb >= Lsb && Bits > Msb)
+ break;
+ return false;
+ }
}
}
diff --git a/llvm/test/CodeGen/RISCV/bitextract-mac.ll b/llvm/test/CodeGen/RISCV/bitextract-mac.ll
index 41a32656e3257..71066b2619cfa 100644
--- a/llvm/test/CodeGen/RISCV/bitextract-mac.ll
+++ b/llvm/test/CodeGen/RISCV/bitextract-mac.ll
@@ -107,7 +107,7 @@ define i32 @f(i32 %A, i32 %B, i32 %C) {
;
; RV64XTHEADBB-LABEL: f:
; RV64XTHEADBB: # %bb.0: # %entry
-; RV64XTHEADBB-NEXT: mul a0, a1, a0
+; RV64XTHEADBB-NEXT: mulw a0, a1, a0
; RV64XTHEADBB-NEXT: th.extu a1, a0, 5, 2
; RV64XTHEADBB-NEXT: th.extu a0, a0, 11, 5
; RV64XTHEADBB-NEXT: mul a0, a1, a0
@@ -116,7 +116,7 @@ define i32 @f(i32 %A, i32 %B, i32 %C) {
;
; RV64XTHEAD-LABEL: f:
; RV64XTHEAD: # %bb.0: # %entry
-; RV64XTHEAD-NEXT: mul a0, a1, a0
+; RV64XTHEAD-NEXT: mulw a0, a1, a0
; RV64XTHEAD-NEXT: th.extu a1, a0, 5, 2
; RV64XTHEAD-NEXT: th.extu a0, a0, 11, 5
; RV64XTHEAD-NEXT: th.mulah a2, a1, a0
diff --git a/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll b/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
index 908a12331d1bb..c253382d3aac9 100644
--- a/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
+++ b/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
@@ -2438,7 +2438,7 @@ define i16 @test_ctpop_i16(i16 %a) nounwind {
; RV64XTHEADBB-NEXT: and a0, a0, a2
; RV64XTHEADBB-NEXT: add a0, a1, a0
; RV64XTHEADBB-NEXT: srli a1, a0, 4
-; RV64XTHEADBB-NEXT: add a0, a0, a1
+; RV64XTHEADBB-NEXT: addw a0, a0, a1
; RV64XTHEADBB-NEXT: th.extu a1, a0, 11, 8
; RV64XTHEADBB-NEXT: andi a0, a0, 15
; RV64XTHEADBB-NEXT: add a0, a0, a1
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These instructions are being used by the scalar efficiency SIG to determine if we should have a standard instruction. Improving our support for these instructions may give better data for their analysis.
I'll follow up by adding this to RISCVOptWInstrs too which will remove the 'w' suffixes added here.