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shared/runtime/semihosting: Add RISC-V semihosting code. #15097

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Merged
merged 2 commits into from
Jun 6, 2024

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agatti
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@agatti agatti commented May 22, 2024

This PR contains a full-featured RISC-V semihosting interface implementation.

Even though it targets RISC-V, the specifications say they follow Arm's semihosting call interface and thus this bit of code can be easily modified to also support Arm/Thumb and Aarch64. To keep breakages at a minimum to users of the Arm-specific semihosting code I chose to put this in a different file instead, plus there are no guarantees they

If needed I can make the necessary modifications to have one single RV32/RV64/Aarch32/Aarch64 semihosting implementation, although there are no guarantees they won't diverge in the future (the RISC-V specifications are at version 0.3, after all...)

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Code size report:

   bare-arm:    +0 +0.000% 
minimal x86:    +0 +0.000% 
   unix x64:    +0 +0.000% standard
      stm32:    +0 +0.000% PYBV10
     mimxrt:    +0 +0.000% TEENSY40
        rp2:    +0 +0.000% RPI_PICO
       samd:    +0 +0.000% ADAFRUIT_ITSYBITSY_M4_EXPRESS

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dpgeorge commented Jun 5, 2024

Did you implement all of this code yourself, from scratch? (We need to be careful with licensing/copyright.)

And did you make use of this (or test it) with your qemu-riscv work #12853?

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agatti commented Jun 5, 2024

Yes I did write it myself. If you prefer a more authoritative source I guess you can take Arm's implementation and simply replace the entry call with the one provided by the RISC-V specification. This specification is actually quite simple to implement.

For testing, I used it quite a bit when debugging my code emitter (heap dumping and file I/O), although I haven't tested more exotic calls like get command line, elapsed time, invoke system command, etc. Fun fact, QEMU switches stack start and stack limit pointers in the structure when calling get heap info.

Haven't tested it on OpenOCD, but I guess its implementation should be at least as complete as QEMU's.

@dpgeorge dpgeorge added the shared Relates to shared/ directory in source label Jun 6, 2024
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dpgeorge commented Jun 6, 2024

OK, thanks for the clarifications. I'm happy to merge this, since it's useful for debugging.

agatti added 2 commits June 6, 2024 12:55
Make room for RISC-V semihosting code, by renaming the existing
`semihosting.[ch]` files into `semihosting_arm.[ch]`.

Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
This adds a RISC-V RV32 semihosting implementation, with all defined
system calls exposed to the user.

Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
@dpgeorge dpgeorge force-pushed the semihosting-riscv branch from 63ed9db to ace08c3 Compare June 6, 2024 02:55
@dpgeorge dpgeorge merged commit ace08c3 into micropython:master Jun 6, 2024
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@agatti agatti deleted the semihosting-riscv branch June 6, 2024 05:16
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