Draft Catch and raise deadlock in adc config. #16808
Open
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
|
Code size report: |
679934b to
ebfa7a9
Compare
Signed-off-by: Andrew Leech <andrew.leech@planetinnovation.com.au>
ebfa7a9 to
74cf14b
Compare
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Summary
Seen on a project using the stm32wb55 occasionally the device was locking up, pausing on the attached debugger showed the code was stuck in this while loop waiting for the ADC to report ready which never occurred.
The ADC read in progress was of a pin that's regularly read in a looping async task, normally operates fine.
The lockup was a number of times in the same place, in all cases it seemed to occur shortly after a cpu speed change.
Testing
I've not been able to reliably reproduce the original failure so I'm not yet certain if this exception raise works as expected.
After the issue occurs I'm not sure if re-trying the ADC read is enough to get it working or whether some broader reset of the ADC is required.
Trade-offs and Alternatives
If the issue is caused by the cpu speed change then some kind of ADC block / clock reset might be possible at a lower level as part of the speed change logic.