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mimxrt: Three bug fixes, another board and consistency changes. #8359

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robert-hh
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@robert-hh robert-hh commented Feb 26, 2022

This is another service type PR for the MIMXRT port.

  • Change two GPIO init calls to the common call type in
    machine_spi.c. No functional change, no API change.
  • Add board files for the MIMXRT1015_EVK board.
  • Wait, if no buffers are available, when sending over Ethernet,
    Before, a BUFERR was returned. Now the code waits up to 1 ms
    for a free buffer. That's sufficient. Usually there is a buffer
    available in less than 100µs.
  • Use the same SPI1 pins for Teensy 4.0 and Teensy 4.1.
  • Change boards/manifest.py to include a board-specific manifest.py,
    if present.
  • Avoid a race condition in Ethernet. That could happen when sending
    at the fastest rate. Typically that happened after >100MByte data
    being sent.
  • Some small improvements for PWM.
    a) Fix the duty rate symmetry of PWM. The X and Q channels were off
    by a count of 1, which was evident at high PWM frequencies like
    15 MHz with small dividers.
    b) Round up or down non-integral division factors to the closest integer.
    Before, always the floor value was used.

The method was changed, but not for the CSx pins. No functional change.
OCOTP_Init() has been removed from mphalport.c. The library files
are missing for the MIMXRT1015, and for just reading the OCOTP
the Init is not required.
Sometimes frames could not be sent immediately because the controller
was still busy with previous frames. Then, an error was returned to
lwip. This fix adds a limited number of retries for this busy state,
waiting 100µs before the next attempt. Typically the transmit succeeds
now at the second attempt.

Second change: Reset the controller for a clean state after soft reset.
Teensy 4.1 used different pins for SPI1 than Teensy 4.0. That
caused irrtitations. So I propose to change it.
If the board directory contains a manifest.py file, it will be
included. File not found errors will be ignored.
That caused Ethernet to lock up at high data rates after ~200MByte
data average in a row. Tested now with data bursts up to 10 GByte and
overall data rates of ~8MByte/s at the Eth100 port.
- Ensure the symmetry of PWM.
  The duty rate of X and Q channels was not 50%, when it should have been.
  That is evident at high frequencies, like 15Mhz of 37.5 MHz. At low
  frequencies the deviation mattered less. The A/B channels were fine.
- Round up or down non-integer division factors. Before, always the
  floor value was used.
@dpgeorge
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dpgeorge commented Mar 8, 2022

Thanks, this all looks good. Merged in 5cc50b9 through e0b9701

@dpgeorge dpgeorge closed this Mar 8, 2022
@robert-hh
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Thanks.

@robert-hh robert-hh deleted the mimxrt_various5 branch March 9, 2022 19:18
tannewt pushed a commit to tannewt/circuitpython that referenced this pull request Feb 15, 2024
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