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Interpret str-type args to interconnect as non-sequence #698

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Merged
merged 1 commit into from
Jan 30, 2022
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Interpret str-type args to interconnect as non-sequence #698

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5 changes: 5 additions & 0 deletions control/iosys.py
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Original file line number Diff line number Diff line change
Expand Up @@ -2519,6 +2519,11 @@ def interconnect(syslist, connections=None, inplist=[], outlist=[],
# Use an empty connections list
connections = []

if isinstance(inputs, str):
inputs = [inputs]
if isinstance(outputs, str):
outputs = [outputs]

# If inplist/outlist is not present, try using inputs/outputs instead
if not inplist and inputs is not None:
inplist = list(inputs)
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20 changes: 20 additions & 0 deletions control/tests/interconnect_test.py
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Expand Up @@ -210,3 +210,23 @@ def test_interconnect_exceptions():

with pytest.raises(TypeError, match="unknown parameter"):
sumblk = ct.summing_junction(input_count=2, output_count=2)


def test_string_inputoutput():
# regression test for gh-692
P1 = ct.rss(2, 1, 1)
P1_iosys = ct.LinearIOSystem(P1, inputs='u1', outputs='y1')
P2 = ct.rss(2, 1, 1)
P2_iosys = ct.LinearIOSystem(P2, inputs='y1', outputs='y2')

P_s1 = ct.interconnect([P1_iosys, P2_iosys], inputs='u1', outputs=['y2'])
assert P_s1.input_index == {'u1' : 0}

P_s2 = ct.interconnect([P1_iosys, P2_iosys], input='u1', outputs=['y2'])
assert P_s2.input_index == {'u1' : 0}

P_s1 = ct.interconnect([P1_iosys, P2_iosys], inputs=['u1'], outputs='y2')
assert P_s1.output_index == {'y2' : 0}

P_s2 = ct.interconnect([P1_iosys, P2_iosys], inputs=['u1'], output='y2')
assert P_s2.output_index == {'y2' : 0}