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[ci] Add riscv opt-int build #143979
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[ci] Add riscv opt-int build #143979
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🔗 Helpful Links🧪 See artifacts and rendered test results at hud.pytorch.org/pr/143979
Note: Links to docs will display an error until the docs builds have been completed. ✅ You can merge normally! (1 Unrelated Failure)As of commit 52dea10 with merge base 33a1996 ( UNSTABLE - The following job is marked as unstable, possibly due to flakiness on trunk:
This comment was automatically generated by Dr. CI and updates every 15 minutes. |
Hi, @malfet Here’s a gentle ping: we have fixed some code errors detected by the CI. When you have time, could you please take a look and provide any suggestions? |
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@Skylion007 Could you help review it if you have time? |
@zhangfeiv0 Do you mind changing it to opt-in only for now and delete binary wheels workflow? Let's see if builds are passing first and than we can take next steps. |
@pytorchbot rebase |
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@pytorchbot rebase |
@pytorchbot started a rebase job onto refs/remotes/origin/viable/strict. Check the current status here |
Successfully rebased |
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@pytorchbot started a rebase job onto refs/remotes/origin/viable/strict. Check the current status here |
Making some changes to the workflow now. If it finished build in reasonable amount of time, than yes, it could be landed as an opt-in for now |
@zhangfeiv0, you'll need to adapt your PR to make it work with CI build, i.e. docker for CI is build using files in |
Successfully rebased |
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export CMAKE_CROSSCOMPILING=TRUE | ||
export CMAKE_SYSTEM_NAME=Linux | ||
export CMAKE_SYSTEM_PROCESSOR=riscv64 |
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IMO if one really cross-compiles, it should be CMAKE_TARGET_PROCESSOR
rather than a system one
During cross-compilation, some third-party libraries need to run on the host machine, including
To address this, I introduced Additionally, some steps you previously deleted need to be retained; otherwise, compilation errors will still occur during the build phase. @malfet Could you restart the workflow and check again? Thanks! |
@malfet bump! |
Shall we rebase this again? @zhangfeiv0 |
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@houseroad Friendly ping |
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Signed-off-by: Zhang fei <zhangfei@iscas.ac.cn>
Signed-off-by: Zhang fei <zhangfei@iscas.ac.cn>
Signed-off-by: Zhang fei <zhangfei@iscas.ac.cn>
Signed-off-by: Zhang fei <zhangfei@iscas.ac.cn>
Signed-off-by: Zhang fei <zhangfei@iscas.ac.cn>
Signed-off-by: Zhang fei <zhangfei@iscas.ac.cn>
Signed-off-by: Zhang fei <zhangfei@iscas.ac.cn>
Signed-off-by: Zhang fei <zhangfei@iscas.ac.cn>
Signed-off-by: Zhang fei <zhangfei@iscas.ac.cn>
Signed-off-by: Zhang fei <zhangfei@iscas.ac.cn>
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Signed-off-by: Zhang fei <zhangfei@iscas.ac.cn>
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Hi, @malfet
Based on the previous discussion:
RISCV CI support · Issue #141550 · pytorch/pytorch
I have cross-compiled PyTorch for the RISC-V architecture on x86_64 Ubuntu 24.04 and created a new PR for it. Could you please help review it?
cc @malfet @seemethere