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Transpiler refactor #1500

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merged 37 commits into from
Nov 27, 2024
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2c7190e
fix: update connectivity in default transpiler
Oct 17, 2024
e1e769a
fix: remove initial_layout & use wire_names & update test files
Oct 22, 2024
2a888ad
fix: update code-examples
Oct 23, 2024
05b6f68
fix: update comparison in test_bell_state_3q
Oct 23, 2024
876b79c
feat: circuit draw with int qubit names
Oct 23, 2024
02e9945
fix: placer.py coverage
Oct 23, 2024
05f36e7
fix: circuit.py coverage
Oct 23, 2024
01b667d
fix: router.py coverage
Oct 23, 2024
4e21132
fix: remove dead codes
Oct 24, 2024
12bf8b0
fix: refactor connectivity graphs in test files
Oct 24, 2024
36c1348
fix: return type of a router
Oct 24, 2024
f19dc6e
fix: minor changes
Oct 25, 2024
7534ef2
fix: remove add_nodes_from when setting backend
Oct 25, 2024
67fae1f
fix: Circuit remove default wire_names / dict wire_names
Oct 28, 2024
2ac1a85
fix: wire_names update docstrings
Oct 28, 2024
788fd06
fix: line connectivity remove fixture
Oct 28, 2024
4e3dbce
fix: test files default qubit
Oct 28, 2024
d4e507c
fix: refactor assert functions
Oct 28, 2024
5cf75b5
fix: refactor assert funcs
Oct 28, 2024
942991a
fix: pandoc update result draw()
Oct 28, 2024
25d8788
fix: pandoc update
Oct 28, 2024
93ac772
feat: Circuit __init__ int/list first arg init
Oct 28, 2024
41f5eff
fix: Circuit._parse -> _resolve_qubits
Oct 28, 2024
a4f2092
fix: minor updates / update docstring of qibo.Circuit
Oct 30, 2024
10be459
fix: update test files _resolve_qubits / wire_names setter
Oct 30, 2024
a1d3302
fix: combine similar assert func to assert_placement
Oct 30, 2024
0851eeb
fix: minor test files update
Oct 30, 2024
ec37f34
Merge branch 'master' into transpiler_refactor
Nov 4, 2024
32c9ac2
Merge branch 'master' into transpiler_refactor
csookim Nov 8, 2024
ff89c58
Merge branch 'master' into transpiler_refactor
Nov 19, 2024
824bb76
passes move connectivity check to __call__
Nov 21, 2024
214a4ea
fix: remove Trivial and Custom
Nov 22, 2024
abed4b9
fix: remove default star transpiler / enforce connectivity
Nov 22, 2024
ad079de
fix: modify is_satisfied
Nov 22, 2024
1f55f3c
fix: revert, make connectivity optiona
Nov 22, 2024
797331e
fix: type errors, Preprocessor connectivity check, utils.py -> assert…
Nov 25, 2024
049ff01
fix: utils -> asserts
Nov 25, 2024
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feat: circuit draw with int qubit names
  • Loading branch information
changsookim committed Oct 23, 2024
commit 876b79c2789a7c66c722442829fd8048ed7d2551
7 changes: 4 additions & 3 deletions src/qibo/models/circuit.py
Original file line number Diff line number Diff line change
Expand Up @@ -1280,6 +1280,7 @@ def diagram(self, line_wrap: int = 70, legend: bool = False) -> str:
"""Build the string representation of the circuit diagram."""
# build string representation of gates
matrix = [[] for _ in range(self.nqubits)]
wire_names = [str(name) for name in self.wire_names]
idx = [0] * self.nqubits

for gate in self.queue:
Expand All @@ -1301,12 +1302,12 @@ def diagram(self, line_wrap: int = 70, legend: bool = False) -> str:
matrix[row][col] += "─" * (1 + maxlen - len(matrix[row][col]))

# Print to terminal
max_name_len = max(len(name) for name in self.wire_names)
max_name_len = max(len(name) for name in wire_names)
output = ""
for q in range(self.nqubits):
output += (
self.wire_names[q]
+ " " * (max_name_len - len(self.wire_names[q]))
wire_names[q]
+ " " * (max_name_len - len(wire_names[q]))
+ ": ─"
+ "".join(matrix[q])
+ "\n"
Expand Down
18 changes: 18 additions & 0 deletions tests/test_models_circuit.py
Original file line number Diff line number Diff line change
Expand Up @@ -667,6 +667,24 @@ def test_circuit_draw_wire_names():
assert str(circuit) == ref


def test_circuit_draw_wire_names_int():
ref = (
"2133: ─H─U1─U1─U1─U1───────────────────────────x───\n"
+ "8 : ───o──|──|──|──H─U1─U1─U1────────────────|─x─\n"
+ "2319: ──────o──|──|────o──|──|──H─U1─U1────────|─|─\n"
+ "0 : ─────────o──|───────o──|────o──|──H─U1───|─x─\n"
+ "1908: ────────────o──────────o───────o────o──H─x───"
)
circuit = Circuit(5, wire_names=[2133, 8, 2319, 0, 1908])
for i1 in range(5):
circuit.add(gates.H(i1))
for i2 in range(i1 + 1, 5):
circuit.add(gates.CU1(i2, i1, theta=0))
circuit.add(gates.SWAP(0, 4))
circuit.add(gates.SWAP(1, 3))
assert str(circuit) == ref


def test_circuit_draw_line_wrap(capsys):
"""Test circuit text draw with line wrap."""
ref_line_wrap_50 = (
Expand Down