All bytes of the supervisor-level iprio array are read-only 0s, and
stopi.IPRIO is always 1 whenever stopi is not 0.

…and hviprio2h CSRs)

AIA introduces the concept of inaccessible CSR, where accessing from
M-mode or HS-mode raises an illegal instruction exception, but doing so
from VS-mode or VU-mode raises a virtual instruction exception.

Without IMSIC, mtopei and stopei do not exist. In contrast, vstopei is
an inaccessible CSR even without IMSIC, i.e., exits and is HS-qualified.

In summary, accessing stopei from M-mode or HS-mode (v=0) raises illegal
instruction, and accessing stopei (actually vstopei) from VS-mode or
VU-mode (v=1) raises virtual instruction.

The pair hvictl.IID=9 and hvictl.IPRIO=0 generally represent no
interrupt in hvictl.

While zeroing also signifies no interrupt, this intermediate commit in
the AIA series aims to explicitly state the absence of an interrupt
condition to prevent confusion in subsequent intermediate commits.

…al_permission_csr_t

… or siph) from VS-mode when hvictl.VTI=1

…ph) from VS-mode when hvictl.VTI=1

If hvictl.VTI=0, vstopi returns information about the highest-priority
pending-and-enabled major interrupt indicated by vsip and vsie.

If hvictl.VTI=1, vstopi return information about a supervisor extenal
interrupt if bit 9 is one in both vsip and vsie.

If hvictl.VTI=1, there are two interrupt candidates for VS level. One is
a supervisor extenal interrupt if bit 9 is one in both vsip and vsie.
The other one is specified by hvictl.IID if hvictl.IID is not 9. The
hvictl.DPR determines the priority order between two interrupts.

If hvictl.IPRIOM=1, vstopi.IPRIO indicates the priority of the
highest-priority interrupt if vstopi is nonzero.

For a supervisor external interrupt, vstopi.IPRIO is hvictl.IPRIO if
hvictl.IID=9 and hvictl.IPRIO!=0; otherwise, vstopi.IPRIO is 255.

For other interrupts under hvictl.VTI=1, vstopi.IPRIO is 0 if
hvictl.iprio=0 and hvictl.dpr=0; vstopi.IPRIO is hvictl.iprio if
hvictl.iprio!=0; vstopi.IPRIO is 255 if hvictl.iprio=0 and hvictl.dpr=1.

For other interrupts under hvictl.VTI=0, vstopi.IPRIO is 255 (lowest
priority). That is because other interrupts have the same priority value
0 due to hviprio1=hviprio2=0. In other words, the hvictl.IPRIO of other
interrupts is determined by the default priority, which is lower than
the SEI with the lowest priority value 255.

… in mideleg remain 0s (interrupt filtering)

The modification is backward compatible because mvien is implicitly 0
without AIA.

An interrupt is pending at VS level if and only if vstopi is not 0.

The modification is backward compatible because hvictl is implicitly 0
without AIA.

…v)sireg

… hviprio[12](h), and supervisor-level iprio array

…, (v)sieh, hidelegh, and hviph