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Merge #715 #725
715: Fix various issues with STM32L562 r=adamgreig a=sphw This PR fixes two issues with the STM32L562's SVD files. In particular the DMA registers CCR registers only included the correct fields on the first register. This PR fixes that. It also merges the GTZC VCTR into an array, rather than individual fields. 725: f7 jpeg mem r=adamgreig a=burrbull Co-authored-by: Sascha Wise <me@saschawise.com> Co-authored-by: Adam Greig <adam@adamgreig.com> Co-authored-by: Andrey Zgarbul <zgarbul.andrey@gmail.com>
3 parents fa72d11 + 7548836 + 353f0ec commit 039f944

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5 files changed

+198
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‎devices/common_patches/jpeg/ram.yaml

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JPEG:
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_array:
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"QMEM0_*":
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name: QMEM0%s
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"QMEM1_*":
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name: QMEM1%s
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"QMEM2_*":
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name: QMEM2%s
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"QMEM3_*":
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name: QMEM3%s
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"HUFFMIN_*":
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name: HUFFMIN%s
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"HUFFBASE*": {}
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"HUFFSYMB*": {}
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"DHTMEM*": {}
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"HUFFENC_AC0_*":
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name: HUFFENC_AC0%s
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"HUFFENC_AC1_*":
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name: HUFFENC_AC1%s
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"HUFFENC_DC0_*":
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name: HUFFENC_DC0%s
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"HUFFENC_DC1_*":
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name: HUFFENC_DC1%s

‎devices/stm32f765.yaml

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@@ -176,6 +176,7 @@ _include:
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- ../peripherals/eth/eth_mac_cstf.yaml
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- ../peripherals/eth/eth_mmc_common.yaml
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- ../peripherals/eth/eth_mmc_mcfhp_mcp.yaml
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- common_patches/jpeg/ram.yaml
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- ../peripherals/wwdg/wwdg.yaml
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- ../peripherals/pwr/pwr_f7.yaml
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- ../peripherals/pwr/pwr_v2.yaml

‎devices/stm32f7x7.yaml

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@@ -313,6 +313,7 @@ _include:
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- ../peripherals/eth/eth_mac_cstf.yaml
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- ../peripherals/eth/eth_mmc_common.yaml
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- ../peripherals/eth/eth_mmc_mcfhp_mcp.yaml
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- common_patches/jpeg/ram.yaml
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- ../peripherals/wwdg/wwdg.yaml
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- ../peripherals/pwr/pwr_f7.yaml
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- ../peripherals/pwr/pwr_v2.yaml

‎devices/stm32f7x9.yaml

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@@ -320,6 +320,7 @@ _include:
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- ../peripherals/eth/eth_mac_cstf.yaml
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- ../peripherals/eth/eth_mmc_common.yaml
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- ../peripherals/eth/eth_mmc_mcfhp_mcp.yaml
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- common_patches/jpeg/ram.yaml
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- ../peripherals/wwdg/wwdg.yaml
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- ../peripherals/pwr/pwr_f7.yaml
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- ../peripherals/pwr/pwr_v2.yaml

‎devices/stm32l562.yaml

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@@ -9,7 +9,6 @@ _modify:
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fpuPresent: "true"
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nvicPrioBits: 3
1111
vendorSystickConfig: "false"
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FMC:
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_strip:
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- "FMC_"
@@ -29,10 +28,15 @@ PKA:
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GTZC_MPCBB1:
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_strip:
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- "MPCBB1_"
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_array:
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"VCTR*":
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name: VCTR%s
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GTZC_MPCBB2:
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_strip:
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- "MPCBB2_"
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_array:
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"VCTR*":
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name: VCTR%s
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GTZC_TZIC:
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_strip:
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_strip:
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- "TZSC_"
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"DMA[1-2]":
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"CNDTR[2-4]":
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_add:
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NDT:
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description: Number of data to transfer
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bitOffset: 0
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bitWidth: 18
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_delete:
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- MA
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"CNDTR[6-8]":
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_add:
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NDT:
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description: Number of data to transfer
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bitOffset: 0
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bitWidth: 16
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_delete:
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- MA
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# exclude CCR1 and CCR5, since they already contains the correct regs
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"CCR[2-4]":
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_add:
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MEM2MEM:
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description: Memory to memory mode
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bitOffset: 14
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bitWidth: 1
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PL:
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description: Channel priority level
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bitOffset: 12
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bitWidth: 2
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MSIZE:
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description: Memory size
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bitOffset: 10
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bitWidth: 2
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PSIZE:
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description: Peripheral size
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bitOffset: 8
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bitWidth: 2
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MINC:
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description: Memory increment mdoe
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bitOffset: 7
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bitWidth: 1
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PINC:
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description: Peripheral increment mode
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bitOffset: 7
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bitWidth: 1
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CIRC:
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description: Ciruclar mode
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bitOffset: 5
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bitWidth: 1
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DIR:
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description: Data transfer direction
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bitOffset: 4
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bitWidth: 1
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TEIE:
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description: Transfer error interupt enable
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bitOffset: 3
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bitWidth: 1
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HTIE:
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description: Half transfer interrupt enable
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bitOffset: 2
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bitWidth: 1
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TCIE:
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description: Transfer complete interrupt enable
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bitOffset: 1
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bitWidth: 1
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EN:
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description: Channel enable
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bitOffset: 0
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bitWidth: 1
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DBM:
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description: double-buffer mode
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bitOffset: 15
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bitWidth: 1
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CT:
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description: Current target memory of DMA transfer in double-bufer mode
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bitOffset: 16
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bitWidth: 1
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SECM:
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bitOffset: 17
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bitWidth: 1
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SSEC:
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bitOffset: 18
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bitWidth: 1
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DSEC:
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bitOffset: 19
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bitWidth: 1
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PRIV:
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description: privileged mode
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bitOffset: 20
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bitWidth: 1
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_delete:
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- MA
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"CCR[6-8]":
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_add:
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MEM2MEM:
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description: Memory to memory mode
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bitOffset: 14
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bitWidth: 1
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PL:
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description: Channel priority level
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bitOffset: 12
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bitWidth: 2
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MSIZE:
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description: Memory size
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bitOffset: 10
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bitWidth: 2
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PSIZE:
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description: Peripheral size
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bitOffset: 8
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bitWidth: 2
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MINC:
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description: Memory increment mdoe
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bitOffset: 7
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bitWidth: 1
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PINC:
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description: Peripheral increment mode
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bitOffset: 7
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bitWidth: 1
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CIRC:
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description: Ciruclar mode
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bitOffset: 5
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bitWidth: 1
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DIR:
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description: Data transfer direction
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bitOffset: 4
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bitWidth: 1
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TEIE:
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description: Transfer error interupt enable
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bitOffset: 3
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bitWidth: 1
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HTIE:
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description: Half transfer interrupt enable
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bitOffset: 2
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bitWidth: 1
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TCIE:
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description: Transfer complete interrupt enable
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bitOffset: 1
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bitWidth: 1
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EN:
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description: Channel enable
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bitOffset: 0
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bitWidth: 1
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DBM:
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description: double-buffer mode
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bitOffset: 15
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bitWidth: 1
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CT:
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description: Current target memory of DMA transfer in double-bufer mode
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bitOffset: 16
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bitWidth: 1
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SECM:
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bitOffset: 17
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bitWidth: 1
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SSEC:
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bitOffset: 18
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bitWidth: 1
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DSEC:
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bitOffset: 19
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bitWidth: 1
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PRIV:
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description: privileged mode
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bitOffset: 20
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bitWidth: 1
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_delete:
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- MA
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_include:
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- common_patches/dma_interrupt_names.yaml
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- ../peripherals/gpio/gpio_l5.yaml

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