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bors[bot]oldsheep68adamgreig
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Merge #682
682: shorter registernames for stm32l4 devices of the COMP registers + add… r=adamgreig a=oldsheep68 …ing the register descriptions Changes in: crates stm32l4x1, crates stm32l4x2, crates stm32l4x3, crates stm32l4x5, crates stm32l4x6 registers of the comparator have been renamed, example: from comp1_en -> en this makes a more generic use in programming possible Furthermore, the description has been added for all comp During this work, I found the following topics, where I do not know, how to address: 1) Reference Manual RM0394: is valid for: STM32L443 and STM32L433; but I had to add the register description in the device descriptors stm32l4x3 of RM0351 2) The device STM32L471 is part of stm32l4x1, but is in RM0351 whereas all other devices are part of RM0394 Co-authored-by: oldsheep68 <oldsheep68@hotmail.com> Co-authored-by: Adam Greig <adam@adamgreig.com>
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‎devices/common_patches/comp/l4xx_comp_reg_rename.yaml

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COMP:
2+
COMP1_CSR:
3+
_strip:
4+
- "COMP1_"
5+
COMP2_CSR:
6+
_strip:
7+
- "COMP2_"

‎devices/common_patches/dac/dac_rename_stm32l4xx.yaml

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_modify:
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# Fix DAC peripherals to match other devices
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DAC1:
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name: DAC

‎devices/stm32l4x1.yaml

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@@ -138,3 +138,8 @@ _include:
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- ./common_patches/l4_gpio_brr.yaml
139139
- ./common_patches/l4_tim15_ch2.yaml
140140
- ../peripherals/spi/spi_l4.yaml
141+
- ./common_patches/comp/l4xx_comp_reg_rename.yaml
142+
- ../peripherals/comp/comp_l4x1.yaml
143+
- ./common_patches/dac/dac_rename_stm32l4xx.yaml
144+
- ../peripherals/dac/dac_l4xx.yaml
145+
- ../peripherals/opamp/opamp_l4.yaml

‎devices/stm32l4x2.yaml

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@@ -3,6 +3,7 @@ _svd: ../svd/stm32l4x2.svd
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MPU:
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_strip:
55
- "MPU_"
6+
67

78
# Most of the patches and includes for this device are shared with the L412,
89
# so update the common patch file below instead.
@@ -13,3 +14,8 @@ _include:
1314
- ../peripherals/fw/fw_l0_l4.yaml
1415
- ../peripherals/rcc/rcc_l4_usart2_3.yaml
1516
- ../peripherals/rcc/rcc_l4_uart4.yaml
17+
- ./common_patches/comp/l4xx_comp_reg_rename.yaml
18+
- ../peripherals/comp/comp_l4x1.yaml
19+
- ./common_patches/dac/dac_rename_stm32l4xx.yaml
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- ../peripherals/dac/dac_l4xx.yaml
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- ../peripherals/opamp/opamp_l4.yaml

‎devices/stm32l4x3.yaml

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@@ -168,3 +168,8 @@ _include:
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- ./common_patches/l4_gpio_brr.yaml
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- ../peripherals/spi/spi_l4.yaml
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- ./common_patches/l4_lcd_segment.yaml
171+
- ./common_patches/comp/l4xx_comp_reg_rename.yaml
172+
- ../peripherals/comp/comp_l4x6.yaml
173+
- ./common_patches/dac/dac_rename_stm32l4xx.yaml
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- ../peripherals/dac/dac_l4xx.yaml
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- ../peripherals/opamp/opamp_l4.yaml

‎devices/stm32l4x5.yaml

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@@ -200,3 +200,8 @@ _include:
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- ../peripherals/spi/spi_l4.yaml
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- ./common_patches/l4_tim15_ch2.yaml
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- common_patches/adc_common_group_name.yaml
203+
- ./common_patches/comp/l4xx_comp_reg_rename.yaml
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- ../peripherals/comp/comp_l4x6.yaml
205+
- ./common_patches/dac/dac_rename_stm32l4xx.yaml
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- ../peripherals/dac/dac_l4xx.yaml
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- ../peripherals/opamp/opamp_l4.yaml

‎devices/stm32l4x6.yaml

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@@ -94,3 +94,8 @@ _include:
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- ./common_patches/l4_dbg_apb_fzr_rename.yaml
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- ./common_patches/l4_lcd_segment.yaml
9696
- common_patches/adc_common_group_name.yaml
97+
- ./common_patches/comp/l4xx_comp_reg_rename.yaml
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- ../peripherals/comp/comp_l4x6.yaml
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- ../peripherals/dac/dac_l4xx.yaml
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- ../peripherals/opamp/opamp_l4.yaml
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‎peripherals/comp/comp_l4x1.yaml

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COMP:
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COMP?_CSR:
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# LOCK:
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# Unlocked: [0, "Comparator CSR bits are read-write"]
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# Locked: [1, "Comparator CSR bits are read-only"]
6+
#COMP?_VALUE:
7+
VALUE:
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Low: [0, "Comparator output is low"]
9+
High: [1, "Comparator output is high"]
10+
SCALEN:
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Disabled: [0, "Voltage scaler disabled"]
12+
Enabled: [1, "Voltage scaler enabled"]
13+
BRGEN:
14+
Disabled: [0, "Scaler resistor bridge disabled"]
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Enabled: [1, "Scaler resistor bridge enabled"]
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BLANKING:
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NoBlanking: [0, "No blanking"]
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TIM1OC5: [4, "TIM15 OC1 selected as blanking source"]
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HYST:
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NoHysteresis: [0, "No hysteresis"]
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LowHysteresis: [1, "Low hysteresis"]
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MediumHysteresis: [2, "Medium hysteresis"]
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HighHysteresis: [3, "High hysteresis"]
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POLARITY:
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NotInverted: [0, "Output is not inverted"]
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Inverted: [1, "Output is inverted"]
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PWRMODE:
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HighSpeed: [0, "High speed / full power"]
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MediumSpeed: [1, "Medium speed / medium power"]
30+
LowSpeed: [3, "Low speed / ultra-low power"]
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EN:
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Disabled: [0, "Comparator 1 disabled"]
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Enabled: [1, "Comparator 1 enabled"]
34+
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COMP1_CSR:
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INPSEL:
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PC5: [0, "PC5 connected to input plus"]
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PB2: [1, "PB2 connected to input plus"]
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PA3: [2, "PA3 connected to input plus"]
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INMSEL:
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OneQuarterVRef: [0, "1/4 of VRefint"]
42+
OneHalfVRef: [1, "1/2 of VRefint"]
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ThreeQuarterVRef: [2, "3/4 of VRefint"]
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VRef: [3, "VRefint"]
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DAC_CH1: [4, "DAC Channel 1"]
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DAC_CH2: [5, "DAC Channel 2"]
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GPIOx: [6, "GPIO selected with INMESEL"]
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INMESEL:
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PC4: [0, "PC4"]
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PA0: [1, "PA0"]
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PA4: [2, "PA4"]
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PA5: [3, "PA5"]
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COMP2_CSR:
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WINMODE:
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Disabled: [0, "COMP2 input plus is not connected to COMP1"]
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Enabled: [1, "COMP2 input plus is connected to COMP1 plus"]
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INPSEL:
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PB4: [0, "PB4 connected to input plus"]
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PB6: [1, "PB6 connected to input plus"]
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PA3: [2, "PA3 connected to input plus"]
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INMSEL:
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OneQuarterVRef: [0, "1/4 of VRefint"]
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OneHalfVRef: [1, "1/2 of VRefint"]
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ThreeQuarterVRef: [2, "3/4 of VRefint"]
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VRef: [3, "VRefint"]
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DAC_CH1: [4, "DAC Channel 1"]
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DAC_CH2: [5, "DAC Channel 2"]
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PB3: [6, "PB3"]
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GPIOx: [7, "GPIO selected by INMESEL"]
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INMESEL:
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PB7: [0, "PB7"]
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PA2: [1, "PA2"]
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PA4: [2, "PA4"]
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PA5: [3, "PA5"]

‎peripherals/comp/comp_l4x6.yaml

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COMP:
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COMP?_CSR:
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# LOCK:
4+
# Unlocked: [0, "Comparator CSR bits are read-write"]
5+
# Locked: [1, "Comparator CSR bits are read-only"]
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#COMP?_VALUE:
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VALUE:
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Low: [0, "Comparator output is low"]
9+
High: [1, "Comparator output is high"]
10+
SCALEN:
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Disabled: [0, "Voltage scaler disabled"]
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Enabled: [1, "Voltage scaler enabled"]
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BRGEN:
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Disabled: [0, "Scaler resistor bridge disabled"]
15+
Enabled: [1, "Scaler resistor bridge enabled"]
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BLANKING:
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NoBlanking: [0, "No blanking"]
18+
TIM1OC5: [4, "TIM15 OC1 selected as blanking source"]
19+
HYST:
20+
NoHysteresis: [0, "No hysteresis"]
21+
LowHysteresis: [1, "Low hysteresis"]
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MediumHysteresis: [2, "Medium hysteresis"]
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HighHysteresis: [3, "High hysteresis"]
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POLARITY:
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NotInverted: [0, "Output is not inverted"]
26+
Inverted: [1, "Output is inverted"]
27+
PWRMODE:
28+
HighSpeed: [0, "High speed / full power"]
29+
MediumSpeed: [1, "Medium speed / medium power"]
30+
LowSpeed: [3, "Low speed / ultra-low power"]
31+
EN:
32+
Disabled: [0, "Comparator 1 disabled"]
33+
Enabled: [1, "Comparator 1 enabled"]
34+
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COMP1_CSR:
36+
INPSEL:
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PC5: [0, "PC5 connected to input plus"]
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PB2: [1, "PB2 connected to input plus"]
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INMSEL:
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OneQuarterVRef: [0, "1/4 of VRefint"]
41+
OneHalfVRef: [1, "1/2 of VRefint"]
42+
ThreeQuarterVRef: [2, "3/4 of VRefint"]
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VRef: [3, "VRefint"]
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DAC_CH1: [4, "DAC Channel 1"]
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DAC_CH2: [5, "DAC Channel 2"]
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PC4: [6, "PC4"]
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48+
COMP2_CSR:
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WINMODE:
50+
Disabled: [0, "COMP2 input plus is not connected to COMP1"]
51+
Enabled: [1, "COMP2 input plus is connected to COMP1 plus"]
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INPSEL:
53+
PB4: [0, "PB4 connected to input plus"]
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PB6: [1, "PB6 connected to input plus"]
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INMSEL:
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OneQuarterVRef: [0, "1/4 of VRefint"]
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OneHalfVRef: [1, "1/2 of VRefint"]
58+
ThreeQuarterVRef: [2, "3/4 of VRefint"]
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VRef: [3, "VRefint"]
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DAC_CH1: [4, "DAC Channel 1"]
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DAC_CH2: [5, "DAC Channel 2"]
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PB3: [6, "PB3"]
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PB7: [7, "PB7"]

‎peripherals/dac/dac_l4xx.yaml

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DAC,DAC?:
2+
"CR,CR?":
3+
"CEN?":
4+
Normal: [0, 'DAC Channel X Normal operating mode']
5+
Calibration: [1, 'DAC Channel X calibration mode']
6+
"DMAUDRIE?":
7+
Disabled: [0, "DAC Channel X DMA Underrun Interrupt disabled"]
8+
Enabled: [1, "DAC Channel X DMA Underrun Interrupt enabled"]
9+
"DMAEN?":
10+
Disabled: [0, "DAC Channel X DMA mode disabled"]
11+
Enabled: [1, "DAC Channel X DMA mode enabled"]
12+
"MAMP?":
13+
Amp1: [0b0000, 'Unmask bit0 of LFSR/ triangle amplitude equal to 1']
14+
Amp3: [0b0001, 'Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3']
15+
Amp7: [0b0010, 'Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7']
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Amp15: [0b0011, 'Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15']
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Amp31: [0b0100, 'Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31']
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Amp63: [0b0101, 'Unmask bits[5:0] of LFSR/ triangle amplitude equal 63']
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Amp127: [0b0110, 'Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127']
20+
Amp255: [0b0111, 'Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255']
21+
Amp511: [0b1000, 'Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511']
22+
Amp1023: [0b1001, 'Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023']
23+
Amp2047: [0b1010, 'Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047']
24+
Amp4095: [0b1011, 'Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095']
25+
"WAVE?":
26+
Disabled: [0, 'Wave generation disabled']
27+
Noise: [1, 'Noise wave generation enabled']
28+
Triangle: [2, 'Triangle wave generation enabled']
29+
"TSEL?":
30+
TIM6_TRGO: [0, 'TIM6_TRGO event trigger for DAC conversion, if TEN is enabled']
31+
TIM8_TRGO: [1, 'TIM8_TRGO']
32+
TIM7_TRGO: [2, 'TIM7_TRGO (Note: Reserved on STM32L45xxx and STM32L46xxx devices)']
33+
TIM5_TRGO: [3, 'TIM5_TRGO']
34+
TIM2_TRGO: [4, 'TIM2_TRGO']
35+
TIM4_TRGO: [5, 'TIM4_TRGO']
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EXTI9: [6, 'External pin']
37+
SWTRIG: [7, 'Software triger']
38+
"TEN?":
39+
Disabled: [0, "DAC Channel X trigger disabled"]
40+
Enabled: [1, "DAC Channel X trigger enabled"]
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"EN?":
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Disabled: [0, "DAC Channel X disabled"]
43+
Enabled: [1, "DAC Channel X enabled"]
44+
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SWTRIGR:
46+
"SWTRIG?":
47+
NoTrigger: [0, 'No trigger']
48+
Trigger: [1, 'Trigger']
49+
50+
"DOR?":
51+
"DACC?DOR": [0, 4095]
52+
53+
SR:
54+
"BWST?":
55+
Idle: [0, 'There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written']
56+
Busy: [1, 'There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written']
57+
"CAL_FLAG?":
58+
Lower: [0, 'Calibration trimming value is lower than the offset correction value']
59+
Equal_Higher: [1, 'Calibration trimming value is equal or greater than the offset correction value']
60+
"DMAUDR?":
61+
NoError: [0, 'No DMA underrun error condition occurred for DAC channel x']
62+
Error: [1, 'DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)']
63+
64+
CCR:
65+
"OTRIM?": [0, 31]
66+
67+
MCR:
68+
"MODE?":
69+
NormalPinBuffer: [0b000, 'Normal mode - DAC channelx is connected to external pin with Buffer enabled']
70+
NormalPinChipBuffer: [0b001, 'Normal mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled']
71+
NormalPinNoBuffer: [0b010, 'Normal mode - DAC channelx is connected to external pin with Buffer disabled']
72+
NormalChipNoBuffer: [0b011, 'Normal mode - DAC channelx is connected to on chip peripherals with Buffer disabled']
73+
SHPinBuffer: [0b100, 'S&H mode - DAC channelx is connected to external pin with Buffer enabled']
74+
SHPinChipBuffer: [0b101, 'S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled']
75+
SHPinNoBuffer: [0b110, 'S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer disabled']
76+
SHChipNoBuffer: [0b111, 'S&H mode - DAC channelx is connected to on chip peripherals with Buffer disabled']
77+
78+
"SHSR?":
79+
"TSAMPLE?": [0, 1023]
80+
81+
SHHR:
82+
"THOLD?": [0, 1023]
83+
84+
SHRR:
85+
"TREFRESH?": [0, 255]
86+
87+
"DHR12R?":
88+
"DACC?DHR": [0, 4095]
89+
90+
"DHR12L?":
91+
"DACC?DHR": [0, 4095]
92+
93+
"DHR8R?":
94+
"DACC?DHR": [0, 255]
95+

‎peripherals/opamp/opamp_l4.yaml

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OPAMP:
3+
OPAMP?_CSR:
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CALOUT: [0, 1]
5+
PGA_GAIN:
6+
Gain2: [0, "Gain 2"]
7+
Gain4: [1, "Gain 4"]
8+
Gain8: [2, "Gain 8"]
9+
Gain16: [3, "Gain 16"]
10+
CALSEL:
11+
NMOS: [0, "0.2V applied to OPAMP inputs during calibration"]
12+
PMOS: [1, VDDA-0.2V applied to OPAMP inputs during calibration"]
13+
CALON:
14+
Disabled: [0, "Normal mode"]
15+
Enabled: [1, "Calibration mode"]
16+
VP_SEL:
17+
GPIO: [0, "GPIO connectet to VINP"]
18+
DAC: [1, "DAC connected to VPINP"]
19+
VM_SEL:
20+
GPIO: [0, "GPIO connectet to VINM"]
21+
LOW_LEAKAGE: [1, "Low leakage inputs connecte (only available in certen BGA cases"]
22+
PGA_MODE: [2, "OPAMP in PGA mode"]
23+
USERTRIM:
24+
Factory: [0, "Factory trim used"]
25+
User: [1, "User trim used"]
26+
OPAMODE:
27+
PGA_DISABLED: [0, "internal PGA diabled"]
28+
PGA_ENABLED: [2, "internal PGA enabled, gain programmed in PGA_GAIN"]
29+
FOLLOWER: [3, "internal follower"]
30+
OPALPM:
31+
NORMAL: [0, OpAmp in normal mode]
32+
LOW: [1, OpAmp in low power mode]
33+
OPAEN:
34+
Disabled: [0, "OpAmp disabled"]
35+
Enabled: [1, "OpAmp enabled"]
36+
OPAMP?_OTR:
37+
TRIMOFFSETN: [0, 31]
38+
TRIMOFFSETP: [0, 31]
39+
OPAMP?_LPOTR:
40+
TRIMLPOFFSETN: [0, 31]
41+
TRIMLPOFFSETP: [0, 31]
42+
43+
OPAMP1_CSR:
44+
OPA_RANGE:
45+
LOW: [0, "low range (VDDA < 2.4V"]
46+
HIGH: [1, "low range (VDDA >2.4V"]
47+

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