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bors[bot]matticoadamgreig
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Merge #499
499: H7B3: Split DAC1/2 REC, remove LPTIM45 r=adamgreig a=mattico Co-authored-by: Matt Ickstadt <mattico8@gmail.com> Co-authored-by: Adam Greig <adam@adamgreig.com>
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devices/stm32h7b3.yaml

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@@ -18,6 +18,76 @@ _modify:
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OctoSPII_O_Manager:
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groupName: OctoSPII_O_Manager
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# Remove LPTIM4/5 from RCC
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# Split DAC1/2 REC
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# TODO: remove LPTIM4/LPTIM5 from EXTI enumerated values
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RCC:
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_modify:
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# Fix reset values for these registers.
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# Note that the rename operation to remove C1 happens alongside this
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# modification, so we have to use the original names.
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C1_APB1LLPENR:
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resetValue: "0xE8FFC3FF"
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C1_APB4ENR:
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resetValue: "0x00010000"
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C1_APB4LPENR:
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resetValue: "0x0C01E6AA"
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APB1LRSTR:
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_modify:
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DAC12RST:
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name: DAC1RST
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description: DAC1 (containing two converters) reset
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APB1LENR:
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_modify:
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DAC12EN:
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name: DAC1EN
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description: DAC1 (containing two converters) peripheral clock enable
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APB1LLPENR:
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_modify:
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DAC12LPEN:
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name: DAC1LPEN
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description: DAC1 (containing two converters) peripheral clock enable during CSleep mode
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APB4RSTR:
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_delete:
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- LPTIM4RST
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- LPTIM5RST
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_add:
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DAC2RST:
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description: DAC2 (containing one converter) reset
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bitOffset: 13
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bitWidth: 1
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access: read-write
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APB4ENR:
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_delete:
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- LPTIM4EN
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- LPTIM5EN
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_add:
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DAC2EN:
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description: DAC2 (containing one converter) peripheral clock enable
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bitOffset: 13
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bitWidth: 1
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access: read-write
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APB4LPENR:
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_delete:
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- LPTIM4LPEN
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- LPTIM5LPEN
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_add:
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DAC2LPEN:
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description: DAC2 (containing one converter) peripheral clock enable during CSleep mode
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bitOffset: 13
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bitWidth: 1
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access: read-write
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D3AMR:
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_delete:
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- LPTIM4AMEN
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- LPTIM5AMEN
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DBGMCU:
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APB4FZ1:
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_delete:
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- LPTIM4
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- LPTIM5
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_include:
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- common_patches/h7_common_highmemory.yaml
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- common_patches/dma_fcr_wo.yaml

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