Merge #552

bors[bot] · andreas-karg-bluefruit · adamgreig · web-flow · commit 970f68f22811 · 2021-10-02T23:42:18.000Z
552: Fix LCD RAM_COM register size on L4x6 r=adamgreig a=AndreasKarg - Make RAM_COM registers bigger - Replace individual segment flags with one 40-bit field # Note If I understand https://www.st.com/content/st_com/en/search.html#q=lcd-t=products-page=1 and the reference manual (RM0351) right, the L4x6 is the only L4 with this LCD peripheral. The SVDs for the 4x1, 2, 3 and 5 seem to contain the same peripheral definition though. Due to this contradiction, I have only applied the patch to the 4x6 for now. If someone could throw another pair of eyes on the documentation and confirm whether the other chips do or don't have this peripheral, I'm happy to update the PR and patch those as well. If it turns out that the SVDs are wrong and the LCD peripherals don't exist, I suggest tackling that in a separate PR. Co-authored-by: Andreas Karg <andreas.karg@bluefruit.co.uk> Co-authored-by: Adam Greig <adam@adamgreig.com>
diff --git a/devices/common_patches/l4_lcd_segment.yaml b/devices/common_patches/l4_lcd_segment.yaml
@@ -0,0 +1,15 @@
+# LCD RAM_COM registers are 64 bit wide, not 32.
+LCD:
+  _modify:
+    RAM_COM?:
+      size: 0x40
+  RAM_COM?:
+    _delete:
+      - "S??"
+    _add:
+      SEGS:
+        description: "Segment states, one bit per segment, LSB: S00, MSB: S39"
+        bitOffset: 0
+        bitWidth: 40
+  _array:
+    "RAM_COM?": {}
diff --git a/devices/stm32l4x3.yaml b/devices/stm32l4x3.yaml
@@ -157,3 +157,4 @@ _include:
  - ./common_patches/l4_adc_sqr1.yaml
  - ./common_patches/l4_spi.yaml
  - ../peripherals/spi/spi_l4.yaml
+ - ./common_patches/l4_lcd_segment.yaml
diff --git a/devices/stm32l4x6.yaml b/devices/stm32l4x6.yaml
@@ -76,3 +76,4 @@ _include:
  - ../peripherals/dma/dma2d_v1.yaml
  - ./common_patches/l4_spi.yaml
  - ../peripherals/spi/spi_l4.yaml
+ - ./common_patches/l4_lcd_segment.yaml
