Skip to content

Fix bit shift in AHB1 register for CRC enable/reset/sleep-mode bits, STM32L4x3.svd patch #517

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 4 commits into from
Mar 28, 2021
Merged

Fix bit shift in AHB1 register for CRC enable/reset/sleep-mode bits, STM32L4x3.svd patch #517

Changes from all commits
Commits
Show all changes
4 commits
Select commit Hold shift + click to select a range
e3106c8
Fix bit shift in AHB1 register for CRC enable/reset/sleep-mode bits
cyrusmetcalf Mar 17, 2021
3aca3ef
Update devices/stm32l4x3.yaml
cyrusmetcalf Mar 24, 2021
2f5b0e5
Update devices/stm32l4x3.yaml
cyrusmetcalf Mar 28, 2021
0dfef36
Merge branch 'master' into merge_branch
cyrusmetcalf Mar 28, 2021
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
17 changes: 17 additions & 0 deletions devices/stm32l4x3.yaml
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -11,13 +11,30 @@ RCC:
USBF:
name: USBFSEN
description: USB FS clock enable


# SVD incorrectly shifts CRCEN/CRCRST/CRCSMEN 11 bits instead of 12
AHB1ENR:
_modify:
CRCEN:
bitOffset: 12
AHB1RSTR:
_modify:
CRCRST:
bitOffset: 12
AHB1SMENR:
_modify:
CRCSMEN:
bitOffset: 12

APB1RSTR1:
_add:
USBFSRST:
description: USB FS reset
bitOffset: 26
bitWidth: 1


_modify:
# The SVD calls ADC1 ADC.
ADC:
Expand Down