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Fix wrong bit offset of CRCEN/CRCRST/CRCSMEN and USARTXSMEN for L4 family #571

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Merged
merged 1 commit into from
Sep 30, 2021

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lulf
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@lulf lulf commented Jun 7, 2021

Various SVD fixes to L4 chips.

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github-actions bot commented Jun 7, 2021

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@lulf lulf changed the title Fix wrong bit offset of CRCEN/CRCRST/CRCSMEN for L4x5 Fix wrong bit offset of CRCEN/CRCRST/CRCSMEN and USARTXSMEN for L4 family Jun 7, 2021
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Thanks for the PR! It all looks correct, except the field at bit 19 of APB1SMENR1 is called UART4SMEN (UART not USART).

This is very tedious, but there's also some very similar errors for L4x1 and L4x2. It would be good to have these in the PR also:

  • Bit 18 of APB1ENR1 should be called USART3EN (3 not 1)
  • Bit 18 of APB1RSTR1 should be called USART3RST (3 not 1)

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lulf commented Jul 8, 2021

@richardeoin Sorry for the late reply. Fixed up the rename.

Regarding the USART1EN -> USART3EN rename, that is already part of the l4x1 and l4x2 patches from what I an see. (Line 12-14 in stm32l4x1.yaml for instance).

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Indeed the USART1EN -> USART3EN rename is being applied for the l4x2 already - I missed that. For the l4x1 it should be applied but the original patches have an error - there's two _add sections, so the first one is being ignored.

Actually this PR has the same error with two _add sections (so USART3SMEN is ignored), which should definitely be fixed.

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@stm32-rs stm32-rs deleted a comment from bors bot Sep 30, 2021
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Thanks, looks good now!

bors r+

@bors bors bot merged commit 0d60821 into stm32-rs:master Sep 30, 2021
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