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Revert rebasing TIM5 for F7x2, since OR must be different. #584

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Merged
merged 1 commit into from
Jul 22, 2021
Merged

Revert rebasing TIM5 for F7x2, since OR must be different. #584

merged 1 commit into from
Jul 22, 2021

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adamgreig
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In #540 TIM5 was updated to be rebased from TIM2, but as its option register OR is different, it can't be rebased.

@burrbull I thought I'd need to instead copy it from TIM2 and then change OR, like

_copy:
  TIM5:
    from: TIM2

TIM5:
  _modify:
    OR:
      description: TIM5 option register 1
  OR:
    _delete:
      - ITR1_RMP
    _add:
      TI4_RMP:
        description: Timer Input 4 remap
        bitOffset: 6
        bitWidth: 2

but it looks like the plain SVD is already correct and we just don't need to do anything, can you remember why you rebased it originally?

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@burrbull
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Sorry. It's my fault. I forgot about OR register.

@adamgreig
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No worries, looks like this fix should be OK then.

@adamgreig adamgreig merged commit 682a2b7 into master Jul 22, 2021
@bors bors bot deleted the f7x2-tim5-or branch July 22, 2021 14:13
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@adamgreig @burrbull