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Updates and fixes for stm32g4xx: FDCAN, FLASH, TIM #668
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Original file line number | Diff line number | Diff line change |
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@@ -4,6 +4,14 @@ _include: | |
- ./fdcan_common.yaml | ||
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"FDCAN,FDCAN?": | ||
_modify: | ||
CREL: | ||
resetValue: 0x32141218 | ||
PSR: | ||
access: read-only | ||
RXF0S: | ||
access: read-only | ||
|
||
RXGFC: | ||
_add: | ||
LSE: | ||
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@@ -22,6 +30,32 @@ _include: | |
description: FIFO 1 operation mode | ||
bitOffset: 8 | ||
bitWidth: 1 | ||
_modify: | ||
ANFS: | ||
description: Accept Non-matching frames standard | ||
ANFE: | ||
description: Accept Non-matching frames extended | ||
RRFS: | ||
description: Reject remote frames standard | ||
RRFE: | ||
description: Reject remote frames extended | ||
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||
ANFS: | ||
accept_rx_fifo0: [0b00, "Accept non-matching standard frames in Rx FIFO 0"] | ||
accept_rx_fifo1: [0b01, "Accept non-matching standard frames in Rx FIFO 1"] | ||
reject: [0b10, "Reject non-matching standard frames"] | ||
reject_: [0b11, "Reject non-matching standard frames"] | ||
ANFE: | ||
accept_rx_fifo0: [0b00, "Accept non-matching extended frames in Rx FIFO 0"] | ||
accept_rx_fifo1: [0b01, "Accept non-matching extended frames in Rx FIFO 1"] | ||
reject: [0b10, "Reject non-matching extended frames"] | ||
reject_: [0b11, "Reject non-matching extended frames"] | ||
RRFS: | ||
filter: [0b0, "Filter remote frames with 11-bit standard IDs"] | ||
reject: [0b1, "Reject all remote frames with 11-bit standard IDs"] | ||
RRFE: | ||
filter: [0b0, "Filter remote frames with 29-bit standard IDs"] | ||
reject: [0b1, "Reject remote frames with 29-bit standard IDs"] | ||
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# Interrupt registers are a disaster, start over | ||
IR: | ||
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@@ -260,8 +294,10 @@ _include: | |
TXFQS: | ||
_modify: | ||
TFQPI: | ||
bitOffset: 16 | ||
bitWidth: 2 | ||
TFGI: | ||
bitOffset: 8 | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Looks like these two new |
||
bitWidth: 2 | ||
TFFL: | ||
bitWidth: 3 | ||
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@@ -301,3 +337,76 @@ _include: | |
_modify: | ||
CFIE: | ||
bitWidth: 3 | ||
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ECR: | ||
_modify: | ||
TREC: | ||
name: REC | ||
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HPMS: | ||
_modify: | ||
FIDX: | ||
bitOffset: 8 | ||
bitWidth: 5 | ||
MSI: | ||
bitOffset: 6 | ||
bitWidth: 2 | ||
BIDX: | ||
bitOffset: 0 | ||
bitWidth: 3 | ||
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||
RXF0S: | ||
_modify: | ||
F0PI: | ||
bitOffset: 16 | ||
bitWidth: 2 | ||
F0GI: | ||
bitOffset: 8 | ||
bitWidth: 2 | ||
F0FL: | ||
bitOffset: 0 | ||
bitWidth: 4 | ||
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||
RXF0A: | ||
_modify: | ||
F0AI: | ||
bitOffset: 0 | ||
bitWidth: 3 | ||
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RXF1S: | ||
_delete: | ||
DMS: | ||
_modify: | ||
F1PI: | ||
bitOffset: 16 | ||
bitWidth: 2 | ||
F1GI: | ||
bitOffset: 8 | ||
bitWidth: 2 | ||
F1FL: | ||
bitOffset: 0 | ||
bitWidth: 4 | ||
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RXF1A: | ||
_modify: | ||
F1AI: | ||
bitOffset: 0 | ||
bitWidth: 4 | ||
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TXBC: | ||
_delete: | ||
TFQS: | ||
NDTB: | ||
TBSA: | ||
_modify: | ||
TFQM: | ||
bitOffset: 24 | ||
bitWidth: 1 | ||
TFQM: | ||
fifo: [0b0, "Tx FIFO operation"] | ||
queue: [0b1, "Tx queue operation"] | ||
Comment on lines
+405
to
+407
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. A little block that belongs in peripherals/ because it adds enumerated values (or permitted write ranges) to a field |
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TXEFA: | ||
_modify: | ||
EFAI: | ||
bitWidth: 2 |
Original file line number | Diff line number | Diff line change |
---|---|---|
|
@@ -14,6 +14,76 @@ _derive: | |
OC6M_bit3: | ||
name: OC6M_3 | ||
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CR1: | ||
CKD: | ||
Div1: [0, "t_DTS = t_CK_INT"] | ||
Div2: [1, "t_DTS = 2 × t_CK_INT"] | ||
Div4: [2, "t_DTS = 4 × t_CK_INT"] | ||
CMS: | ||
EdgeAligned: [0, "The counter counts up or down depending on the direction bit"] | ||
CenterAligned1: [1, "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down."] | ||
CenterAligned2: [2, "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up."] | ||
CenterAligned3: [3, "The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down."] | ||
DIR: | ||
Up: [0, "Counter used as upcounter"] | ||
Down: [1, "Counter used as downcounter"] | ||
CEN: | ||
Disabled: [0, "Counter disabled"] | ||
Enabled: [1, "Counter enabled"] | ||
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CCMR1_Output: | ||
OC2PE: | ||
Disabled: [0, "Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately"] | ||
Enabled: [1, "Preload register on CCR2 enabled. Preload value is loaded into active register on each update event"] | ||
CC2S: | ||
Output: [0, "CC2 channel is configured as output"] | ||
OC1PE: | ||
Disabled: [0, "Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately"] | ||
Enabled: [1, "Preload register on CCR1 enabled. Preload value is loaded into active register on each update event"] | ||
CC1S: | ||
Output: [0, "CC1 channel is configured as output"] | ||
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CCMR2_Output: | ||
OC4PE: | ||
Disabled: [0, "Preload register on CCR4 disabled. New values written to CCR4 are taken into account immediately"] | ||
Enabled: [1, "Preload register on CCR4 enabled. Preload value is loaded into active register on each update event"] | ||
CC4S: | ||
Output: [0, "CC4 channel is configured as output"] | ||
OC3PE: | ||
Disabled: [0, "Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately"] | ||
Enabled: [1, "Preload register on CCR3 enabled. Preload value is loaded into active register on each update event"] | ||
CC3S: | ||
Output: [0, "CC3 channel is configured as output"] | ||
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DIER: | ||
TDE: | ||
Disabled: [0, "Trigger DMA request disabled"] | ||
Enabled: [1, "Trigger DMA request enabled"] | ||
"CC?DE": | ||
Disabled: [0, "CCx DMA request disabled"] | ||
Enabled: [1, "CCx DMA request enabled"] | ||
UDE: | ||
Disabled: [0, "Update DMA request disabled"] | ||
Enabled: [1, "Update DMA request enabled"] | ||
TIE: | ||
Disabled: [0, "Trigger interrupt disabled"] | ||
Enabled: [1, "Trigger interrupt enabled"] | ||
"CC?IE": | ||
Disabled: [0, "CCx interrupt disabled"] | ||
Enabled: [1, "CCx interrupt enabled"] | ||
UIE: | ||
Disabled: [0, "Update interrupt disabled"] | ||
Enabled: [1, "Update interrupt enabled"] | ||
Comment on lines
+17
to
+76
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. This is one of those blocks that belongs in peripherals/ because it adds enumerated values (or permitted write ranges) to a field |
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PSC: | ||
_modify: | ||
PSC: | ||
bitOffset: 0 | ||
bitWidth: 16 | ||
_write_constraint: [0, 65535] | ||
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TIM2: | ||
CNT: | ||
_modify: | ||
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@@ -33,15 +103,26 @@ TIM2: | |
CNT: | ||
_modify: | ||
CNT: | ||
bitOffset: 0 | ||
bitWidth: 16 | ||
_write_constraint: [0, 65535] | ||
ARR: | ||
_modify: | ||
ARR: | ||
bitWidth: 20 | ||
bitOffset: 0 | ||
bitWidth: 16 | ||
_write_constraint: [0, 65535] | ||
CCR?: | ||
_modify: | ||
CCR?: | ||
bitWidth: 20 | ||
bitOffset: 0 | ||
bitWidth: 16 | ||
_write_constraint: [0, 65535] | ||
CCR: | ||
bitOffset: 0 | ||
bitWidth: 16 | ||
_write_constraint: [0, 65535] | ||
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_include: | ||
- ../tim_ccr.yaml |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
This is one of those blocks that belongs in
peripherals/
because it adds enumerated values (or permitted write ranges) to a field