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GlobalISel: Preserve load/store metadata in IRTranslator
This was dropping the invariant metadata on dead argument loads, so they weren't deleted. Atomics still need to be fixed the same way. Also, apparently store was never preserving dereferencable which should also be fixed.
1 parent 03a592f commit 0d0fce4

18 files changed

+238
-94
lines changed

‎llvm/include/llvm/CodeGen/TargetLowering.h

Lines changed: 12 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -284,6 +284,18 @@ class TargetLoweringBase {
284284
return getPointerTy(DL);
285285
}
286286

287+
/// This callback is used to inspect load/store instructions and add
288+
/// target-specific MachineMemOperand flags to them. The default
289+
/// implementation does nothing.
290+
virtual MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const {
291+
return MachineMemOperand::MONone;
292+
}
293+
294+
MachineMemOperand::Flags getLoadMemOperandFlags(const LoadInst &LI,
295+
const DataLayout &DL) const;
296+
MachineMemOperand::Flags getStoreMemOperandFlags(const StoreInst &SI,
297+
const DataLayout &DL) const;
298+
287299
virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
288300
return true;
289301
}
@@ -3763,13 +3775,6 @@ class TargetLowering : public TargetLoweringBase {
37633775
return Chain;
37643776
}
37653777

3766-
/// This callback is used to inspect load/store instructions and add
3767-
/// target-specific MachineMemOperand flags to them. The default
3768-
/// implementation does nothing.
3769-
virtual MachineMemOperand::Flags getMMOFlags(const Instruction &I) const {
3770-
return MachineMemOperand::MONone;
3771-
}
3772-
37733778
/// Should SelectionDAG lower an atomic store of the given kind as a normal
37743779
/// StoreSDNode (as opposed to an AtomicSDNode)? NOTE: The intention is to
37753780
/// eventually migrate all targets to the using StoreSDNodes, but porting is

‎llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

Lines changed: 7 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@
1616
#include "llvm/ADT/SmallSet.h"
1717
#include "llvm/ADT/SmallVector.h"
1818
#include "llvm/Analysis/BranchProbabilityInfo.h"
19+
#include "llvm/Analysis/Loads.h"
1920
#include "llvm/Analysis/OptimizationRemarkEmitter.h"
2021
#include "llvm/Analysis/ValueTracking.h"
2122
#include "llvm/CodeGen/Analysis.h"
@@ -858,11 +859,6 @@ static bool isSwiftError(const Value *V) {
858859

859860
bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) {
860861
const LoadInst &LI = cast<LoadInst>(U);
861-
862-
auto Flags = LI.isVolatile() ? MachineMemOperand::MOVolatile
863-
: MachineMemOperand::MONone;
864-
Flags |= MachineMemOperand::MOLoad;
865-
866862
if (DL->getTypeStoreSize(LI.getType()) == 0)
867863
return true;
868864

@@ -881,6 +877,9 @@ bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) {
881877
return true;
882878
}
883879

880+
auto &TLI = *MF->getSubtarget().getTargetLowering();
881+
MachineMemOperand::Flags Flags = TLI.getLoadMemOperandFlags(LI, *DL);
882+
884883
const MDNode *Ranges =
885884
Regs.size() == 1 ? LI.getMetadata(LLVMContext::MD_range) : nullptr;
886885
for (unsigned i = 0; i < Regs.size(); ++i) {
@@ -903,10 +902,6 @@ bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) {
903902

904903
bool IRTranslator::translateStore(const User &U, MachineIRBuilder &MIRBuilder) {
905904
const StoreInst &SI = cast<StoreInst>(U);
906-
auto Flags = SI.isVolatile() ? MachineMemOperand::MOVolatile
907-
: MachineMemOperand::MONone;
908-
Flags |= MachineMemOperand::MOStore;
909-
910905
if (DL->getTypeStoreSize(SI.getValueOperand()->getType()) == 0)
911906
return true;
912907

@@ -926,6 +921,9 @@ bool IRTranslator::translateStore(const User &U, MachineIRBuilder &MIRBuilder) {
926921
return true;
927922
}
928923

924+
auto &TLI = *MF->getSubtarget().getTargetLowering();
925+
MachineMemOperand::Flags Flags = TLI.getStoreMemOperandFlags(SI, *DL);
926+
929927
for (unsigned i = 0; i < Vals.size(); ++i) {
930928
Register Addr;
931929
MIRBuilder.materializePtrAdd(Addr, Base, OffsetTy, Offsets[i] / 8);

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Lines changed: 11 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -4057,12 +4057,6 @@ void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
40574057
SDValue Ptr = getValue(SV);
40584058

40594059
Type *Ty = I.getType();
4060-
4061-
bool isVolatile = I.isVolatile();
4062-
bool isNonTemporal = I.hasMetadata(LLVMContext::MD_nontemporal);
4063-
bool isInvariant = I.hasMetadata(LLVMContext::MD_invariant_load);
4064-
bool isDereferenceable =
4065-
isDereferenceablePointer(SV, I.getType(), DAG.getDataLayout());
40664060
unsigned Alignment = I.getAlignment();
40674061

40684062
AAMDNodes AAInfo;
@@ -4076,6 +4070,8 @@ void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
40764070
if (NumValues == 0)
40774071
return;
40784072

4073+
bool isVolatile = I.isVolatile();
4074+
40794075
SDValue Root;
40804076
bool ConstantMemory = false;
40814077
if (isVolatile)
@@ -4109,6 +4105,10 @@ void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
41094105
SmallVector<SDValue, 4> Values(NumValues);
41104106
SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
41114107
EVT PtrVT = Ptr.getValueType();
4108+
4109+
MachineMemOperand::Flags MMOFlags
4110+
= TLI.getLoadMemOperandFlags(I, DAG.getDataLayout());
4111+
41124112
unsigned ChainI = 0;
41134113
for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
41144114
// Serializing loads here may result in excessive register pressure, and
@@ -4128,16 +4128,6 @@ void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
41284128
PtrVT, Ptr,
41294129
DAG.getConstant(Offsets[i], dl, PtrVT),
41304130
Flags);
4131-
auto MMOFlags = MachineMemOperand::MONone;
4132-
if (isVolatile)
4133-
MMOFlags |= MachineMemOperand::MOVolatile;
4134-
if (isNonTemporal)
4135-
MMOFlags |= MachineMemOperand::MONonTemporal;
4136-
if (isInvariant)
4137-
MMOFlags |= MachineMemOperand::MOInvariant;
4138-
if (isDereferenceable)
4139-
MMOFlags |= MachineMemOperand::MODereferenceable;
4140-
MMOFlags |= TLI.getMMOFlags(I);
41414131

41424132
SDValue L = DAG.getLoad(MemVTs[i], dl, Root, A,
41434133
MachinePointerInfo(SV, Offsets[i]), Alignment,
@@ -4264,12 +4254,7 @@ void SelectionDAGBuilder::visitStore(const StoreInst &I) {
42644254
AAMDNodes AAInfo;
42654255
I.getAAMetadata(AAInfo);
42664256

4267-
auto MMOFlags = MachineMemOperand::MONone;
4268-
if (I.isVolatile())
4269-
MMOFlags |= MachineMemOperand::MOVolatile;
4270-
if (I.hasMetadata(LLVMContext::MD_nontemporal))
4271-
MMOFlags |= MachineMemOperand::MONonTemporal;
4272-
MMOFlags |= TLI.getMMOFlags(I);
4257+
auto MMOFlags = TLI.getStoreMemOperandFlags(I, DAG.getDataLayout());
42734258

42744259
// An aggregate load cannot wrap around the address space, so offsets to its
42754260
// parts don't wrap either.
@@ -4638,7 +4623,7 @@ void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
46384623
auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
46394624
if (I.isVolatile())
46404625
Flags |= MachineMemOperand::MOVolatile;
4641-
Flags |= DAG.getTargetLoweringInfo().getMMOFlags(I);
4626+
Flags |= DAG.getTargetLoweringInfo().getTargetMMOFlags(I);
46424627

46434628
MachineFunction &MF = DAG.getMachineFunction();
46444629
MachineMemOperand *MMO =
@@ -4689,7 +4674,7 @@ void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
46894674
auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
46904675
if (I.isVolatile())
46914676
Flags |= MachineMemOperand::MOVolatile;
4692-
Flags |= DAG.getTargetLoweringInfo().getMMOFlags(I);
4677+
Flags |= DAG.getTargetLoweringInfo().getTargetMMOFlags(I);
46934678

46944679
MachineFunction &MF = DAG.getMachineFunction();
46954680
MachineMemOperand *MMO =
@@ -4735,16 +4720,7 @@ void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
47354720
I.getAlignment() < MemVT.getSizeInBits() / 8)
47364721
report_fatal_error("Cannot generate unaligned atomic load");
47374722

4738-
auto Flags = MachineMemOperand::MOLoad;
4739-
if (I.isVolatile())
4740-
Flags |= MachineMemOperand::MOVolatile;
4741-
if (I.hasMetadata(LLVMContext::MD_invariant_load))
4742-
Flags |= MachineMemOperand::MOInvariant;
4743-
if (isDereferenceablePointer(I.getPointerOperand(), I.getType(),
4744-
DAG.getDataLayout()))
4745-
Flags |= MachineMemOperand::MODereferenceable;
4746-
4747-
Flags |= TLI.getMMOFlags(I);
4723+
auto Flags = TLI.getLoadMemOperandFlags(I, DAG.getDataLayout());
47484724

47494725
MachineMemOperand *MMO =
47504726
DAG.getMachineFunction().
@@ -4800,10 +4776,7 @@ void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
48004776
if (I.getAlignment() < MemVT.getSizeInBits() / 8)
48014777
report_fatal_error("Cannot generate unaligned atomic store");
48024778

4803-
auto Flags = MachineMemOperand::MOStore;
4804-
if (I.isVolatile())
4805-
Flags |= MachineMemOperand::MOVolatile;
4806-
Flags |= TLI.getMMOFlags(I);
4779+
auto Flags = TLI.getStoreMemOperandFlags(I, DAG.getDataLayout());
48074780

48084781
MachineFunction &MF = DAG.getMachineFunction();
48094782
MachineMemOperand *MMO =

‎llvm/lib/CodeGen/TargetLoweringBase.cpp

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,7 @@
1717
#include "llvm/ADT/StringRef.h"
1818
#include "llvm/ADT/Triple.h"
1919
#include "llvm/ADT/Twine.h"
20+
#include "llvm/Analysis/Loads.h"
2021
#include "llvm/CodeGen/Analysis.h"
2122
#include "llvm/CodeGen/ISDOpcodes.h"
2223
#include "llvm/CodeGen/MachineBasicBlock.h"
@@ -2005,3 +2006,39 @@ int TargetLoweringBase::getDivRefinementSteps(EVT VT,
20052006
void TargetLoweringBase::finalizeLowering(MachineFunction &MF) const {
20062007
MF.getRegInfo().freezeReservedRegs(MF);
20072008
}
2009+
2010+
MachineMemOperand::Flags
2011+
TargetLoweringBase::getLoadMemOperandFlags(const LoadInst &LI,
2012+
const DataLayout &DL) const {
2013+
MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad;
2014+
if (LI.isVolatile())
2015+
Flags |= MachineMemOperand::MOVolatile;
2016+
2017+
if (LI.hasMetadata(LLVMContext::MD_nontemporal))
2018+
Flags |= MachineMemOperand::MONonTemporal;
2019+
2020+
if (LI.hasMetadata(LLVMContext::MD_invariant_load))
2021+
Flags |= MachineMemOperand::MOInvariant;
2022+
2023+
if (isDereferenceablePointer(LI.getPointerOperand(), LI.getType(), DL))
2024+
Flags |= MachineMemOperand::MODereferenceable;
2025+
2026+
Flags |= getTargetMMOFlags(LI);
2027+
return Flags;
2028+
}
2029+
2030+
MachineMemOperand::Flags
2031+
TargetLoweringBase::getStoreMemOperandFlags(const StoreInst &SI,
2032+
const DataLayout &DL) const {
2033+
MachineMemOperand::Flags Flags = MachineMemOperand::MOStore;
2034+
2035+
if (SI.isVolatile())
2036+
Flags |= MachineMemOperand::MOVolatile;
2037+
2038+
if (SI.hasMetadata(LLVMContext::MD_nontemporal))
2039+
Flags |= MachineMemOperand::MONonTemporal;
2040+
2041+
// FIXME: Not preserving dereferenceable
2042+
Flags |= getTargetMMOFlags(SI);
2043+
return Flags;
2044+
}

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9015,7 +9015,7 @@ AArch64TargetLowering::getNumInterleavedAccesses(VectorType *VecTy,
90159015
}
90169016

90179017
MachineMemOperand::Flags
9018-
AArch64TargetLowering::getMMOFlags(const Instruction &I) const {
9018+
AArch64TargetLowering::getTargetMMOFlags(const Instruction &I) const {
90199019
if (Subtarget->getProcFamily() == AArch64Subtarget::Falkor &&
90209020
I.getMetadata(FALKOR_STRIDED_ACCESS_MD) != nullptr)
90219021
return MOStridedAccess;

‎llvm/lib/Target/AArch64/AArch64ISelLowering.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -611,7 +611,8 @@ class AArch64TargetLowering : public TargetLowering {
611611
unsigned getNumInterleavedAccesses(VectorType *VecTy,
612612
const DataLayout &DL) const;
613613

614-
MachineMemOperand::Flags getMMOFlags(const Instruction &I) const override;
614+
MachineMemOperand::Flags getTargetMMOFlags(
615+
const Instruction &I) const override;
615616

616617
bool functionArgumentNeedsConsecutiveRegisters(Type *Ty,
617618
CallingConv::ID CallConv,

‎llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3995,7 +3995,7 @@ SDValue SystemZTargetLowering::lowerATOMIC_CMP_SWAP(SDValue Op,
39953995
}
39963996

39973997
MachineMemOperand::Flags
3998-
SystemZTargetLowering::getMMOFlags(const Instruction &I) const {
3998+
SystemZTargetLowering::getTargetMMOFlags(const Instruction &I) const {
39993999
// Because of how we convert atomic_load and atomic_store to normal loads and
40004000
// stores in the DAG, we need to ensure that the MMOs are marked volatile
40014001
// since DAGCombine hasn't been updated to account for atomic, but non

‎llvm/lib/Target/SystemZ/SystemZISelLowering.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -677,7 +677,8 @@ class SystemZTargetLowering : public TargetLowering {
677677
MachineBasicBlock *MBB,
678678
unsigned Opcode) const;
679679

680-
MachineMemOperand::Flags getMMOFlags(const Instruction &I) const override;
680+
MachineMemOperand::Flags
681+
getTargetMMOFlags(const Instruction &I) const override;
681682
const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
682683
};
683684

‎llvm/lib/Target/XCore/XCoreISelLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -996,7 +996,7 @@ LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const {
996996
}
997997

998998
MachineMemOperand::Flags
999-
XCoreTargetLowering::getMMOFlags(const Instruction &I) const {
999+
XCoreTargetLowering::getTargetMMOFlags(const Instruction &I) const {
10001000
// Because of how we convert atomic_load and atomic_store to normal loads and
10011001
// stores in the DAG, we need to ensure that the MMOs are marked volatile
10021002
// since DAGCombine hasn't been updated to account for atomic, but non

‎llvm/lib/Target/XCore/XCoreISelLowering.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -188,7 +188,8 @@ namespace llvm {
188188
SDValue LowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
189189
SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
190190

191-
MachineMemOperand::Flags getMMOFlags(const Instruction &I) const override;
191+
MachineMemOperand::Flags getTargetMMOFlags(
192+
const Instruction &I) const override;
192193

193194
// Inline asm support
194195
std::pair<unsigned, const TargetRegisterClass *>

‎llvm/test/CodeGen/AArch64/GlobalISel/constant-dbg-loc.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ define i32 @main() #0 !dbg !14 {
1818
; CHECK: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2, debug-location !DILocation(line: 0, scope: !22)
1919
; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.retval
2020
; CHECK: G_STORE [[C]](s32), [[FRAME_INDEX]](p0) :: (store 4 into %ir.retval)
21-
; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0), debug-location !17 :: (load 4 from @var1)
21+
; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0), debug-location !17 :: (dereferenceable load 4 from @var1)
2222
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[LOAD]](s32), [[C1]], debug-location !19
2323
; CHECK: G_BRCOND [[ICMP]](s1), %bb.2, debug-location !20
2424
; CHECK: G_BR %bb.3, debug-location !20

‎llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-load-metadata.ll

Lines changed: 76 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,76 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
; RUN: llc -mtriple=aarch64-- -mcpu=falkor -O0 -aarch64-enable-atomic-cfg-tidy=0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - | FileCheck %s
3+
4+
define i32 @load_invariant(i32* %ptr) {
5+
; CHECK-LABEL: name: load_invariant
6+
; CHECK: bb.1 (%ir-block.0):
7+
; CHECK: liveins: $x0
8+
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
9+
; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (invariant load 4 from %ir.ptr)
10+
; CHECK: $w0 = COPY [[LOAD]](s32)
11+
; CHECK: RET_ReallyLR implicit $w0
12+
%load = load i32, i32* %ptr, align 4, !invariant.load !0
13+
ret i32 %load
14+
}
15+
16+
define i32 @load_volatile_invariant(i32* %ptr) {
17+
; CHECK-LABEL: name: load_volatile_invariant
18+
; CHECK: bb.1 (%ir-block.0):
19+
; CHECK: liveins: $x0
20+
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
21+
; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (volatile invariant load 4 from %ir.ptr)
22+
; CHECK: $w0 = COPY [[LOAD]](s32)
23+
; CHECK: RET_ReallyLR implicit $w0
24+
%load = load volatile i32, i32* %ptr, align 4, !invariant.load !0
25+
ret i32 %load
26+
}
27+
28+
define i32 @load_dereferenceable(i32* dereferenceable(4) %ptr) {
29+
; CHECK-LABEL: name: load_dereferenceable
30+
; CHECK: bb.1 (%ir-block.0):
31+
; CHECK: liveins: $x0
32+
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
33+
; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (dereferenceable load 4 from %ir.ptr)
34+
; CHECK: $w0 = COPY [[LOAD]](s32)
35+
; CHECK: RET_ReallyLR implicit $w0
36+
%load = load i32, i32* %ptr, align 4
37+
ret i32 %load
38+
}
39+
40+
define i32 @load_dereferenceable_invariant(i32* dereferenceable(4) %ptr) {
41+
; CHECK-LABEL: name: load_dereferenceable_invariant
42+
; CHECK: bb.1 (%ir-block.0):
43+
; CHECK: liveins: $x0
44+
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
45+
; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (dereferenceable invariant load 4 from %ir.ptr)
46+
; CHECK: $w0 = COPY [[LOAD]](s32)
47+
; CHECK: RET_ReallyLR implicit $w0
48+
%load = load i32, i32* %ptr, align 4, !invariant.load !0
49+
ret i32 %load
50+
}
51+
52+
define i32 @load_nontemporal(i32* %ptr) {
53+
; CHECK-LABEL: name: load_nontemporal
54+
; CHECK: bb.1 (%ir-block.0):
55+
; CHECK: liveins: $x0
56+
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
57+
; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (non-temporal load 4 from %ir.ptr)
58+
; CHECK: $w0 = COPY [[LOAD]](s32)
59+
; CHECK: RET_ReallyLR implicit $w0
60+
%load = load i32, i32* %ptr, align 4, !nontemporal !0
61+
ret i32 %load
62+
}
63+
64+
define i32 @load_falkor_strided_access(i32* %ptr) {
65+
; CHECK-LABEL: name: load_falkor_strided_access
66+
; CHECK: bb.1 (%ir-block.0):
67+
; CHECK: liveins: $x0
68+
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
69+
; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: ("aarch64-strided-access" load 4 from %ir.ptr)
70+
; CHECK: $w0 = COPY [[LOAD]](s32)
71+
; CHECK: RET_ReallyLR implicit $w0
72+
%load = load i32, i32* %ptr, align 4, !falkor.strided.access !0
73+
ret i32 %load
74+
}
75+
76+
!0 = !{}

‎llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stackprotect-check.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@ define void @foo() ssp {
3232
; CHECK-MIR-NEXT: G_STORE %2(p0), %0(p0) :: (volatile store 8 into %stack.0.StackGuardSlot)
3333
; CHECK-MIR-NEXT: %3:_(p0) = G_FRAME_INDEX %stack.1.buf
3434
; CHECK-MIR-NEXT: %4:gpr64sp(p0) = LOAD_STACK_GUARD :: (dereferenceable invariant load 8 from @__stack_chk_guard)
35-
; CHECK-MIR-NEXT: %5:_(p0) = G_LOAD %0(p0) :: (volatile load 8 from %ir.StackGuardSlot)
35+
; CHECK-MIR-NEXT: %5:_(p0) = G_LOAD %0(p0) :: (volatile dereferenceable load 8 from %ir.StackGuardSlot)
3636
; CHECK-MIR-NEXT: %6:_(s1) = G_ICMP intpred(eq), %4(p0), %5
3737
; CHECK-MIR-NEXT: G_BRCOND %6(s1), %bb.2
3838
; CHECK-MIR-NEXT: G_BR %bb.3

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