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Agilex SDMMC clock enable/disable API #808

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fe51b2a
include: dt-bindings: clk: agilex: Update Agilex clock IDs
Aug 6, 2025
24fb632
drivers: clk: agilex: Support for enable/disable API
Aug 13, 2025
a780b2c
mmc: socfpga_dw_mmc: Enable/disable SDMMC clock via API
Aug 13, 2025
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2 changes: 2 additions & 0 deletions configs/socfpga_agilex_defconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -68,6 +68,8 @@ CONFIG_ENV_UBI_PART="root"
CONFIG_ENV_UBI_VOLUME="env"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_CLK_CCF=y
CONFIG_CLK_CCF=y
CONFIG_SPL_ALTERA_SDRAM=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
Expand Down
120 changes: 120 additions & 0 deletions drivers/clk/altera/clk-agilex.c
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Original file line number Diff line number Diff line change
Expand Up @@ -22,6 +22,8 @@ DECLARE_GLOBAL_DATA_PTR;

struct socfpga_clk_plat {
void __iomem *regs;
int pllgrp;
int bitmask;
};

/*
Expand Down Expand Up @@ -643,8 +645,125 @@ static ulong socfpga_clk_get_rate(struct clk *clk)
}
}

static int bitmask_from_clk_id(struct clk *clk)
{
struct socfpga_clk_plat *plat = dev_get_plat(clk->dev);

switch (clk->id) {
case AGILEX_MPU_CLK:
plat->pllgrp = CLKMGR_MAINPLL_EN;
plat->bitmask = CLKMGR_MAINPLLGRP_EN_MPUCLK_MASK;
break;
case AGILEX_L4_MAIN_CLK:
plat->pllgrp = CLKMGR_MAINPLL_EN;
plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4MAINCLK_MASK;
break;
case AGILEX_L4_MP_CLK:
plat->pllgrp = CLKMGR_MAINPLL_EN;
plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK;
break;
case AGILEX_L4_SP_CLK:
plat->pllgrp = CLKMGR_MAINPLL_EN;
plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4SPCLK_MASK;
break;
case AGILEX_CS_AT_CLK:
plat->pllgrp = CLKMGR_MAINPLL_EN;
plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSCLK_MASK;
break;
case AGILEX_CS_TRACE_CLK:
plat->pllgrp = CLKMGR_MAINPLL_EN;
plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSCLK_MASK;
break;
case AGILEX_CS_PDBG_CLK:
plat->pllgrp = CLKMGR_MAINPLL_EN;
plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSCLK_MASK;
break;
case AGILEX_CS_TIMER_CLK:
plat->pllgrp = CLKMGR_MAINPLL_EN;
plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSTIMERCLK_MASK;
break;
case AGILEX_S2F_USER0_CLK:
plat->pllgrp = CLKMGR_MAINPLL_EN;
plat->bitmask = CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK;
break;
case AGILEX_EMAC0_CLK:
plat->pllgrp = CLKMGR_PERPLL_EN;
plat->bitmask = CLKMGR_PERPLLGRP_EN_EMAC0CLK_MASK;
break;
case AGILEX_EMAC1_CLK:
plat->pllgrp = CLKMGR_PERPLL_EN;
plat->bitmask = CLKMGR_PERPLLGRP_EN_EMAC1CLK_MASK;
break;
case AGILEX_EMAC2_CLK:
plat->pllgrp = CLKMGR_PERPLL_EN;
plat->bitmask = CLKMGR_PERPLLGRP_EN_EMAC2CLK_MASK;
break;
case AGILEX_EMAC_PTP_CLK:
plat->pllgrp = CLKMGR_PERPLL_EN;
plat->bitmask = CLKMGR_PERPLLGRP_EN_EMACPTPCLK_MASK;
break;
case AGILEX_GPIO_DB_CLK:
plat->pllgrp = CLKMGR_PERPLL_EN;
plat->bitmask = CLKMGR_PERPLLGRP_EN_GPIODBCLK_MASK;
break;
case AGILEX_SDMMC_CLK:
plat->pllgrp = CLKMGR_PERPLL_EN;
plat->bitmask = CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK;
break;
case AGILEX_S2F_USER1_CLK:
plat->pllgrp = CLKMGR_PERPLL_EN;
plat->bitmask = CLKMGR_PERPLLGRP_EN_S2FUSER1CLK_MASK;
break;
case AGILEX_PSI_REF_CLK:
plat->pllgrp = CLKMGR_PERPLL_EN;
plat->bitmask = CLKMGR_PERPLLGRP_EN_PSIREFCLK_MASK;
break;
case AGILEX_USB_CLK:
plat->pllgrp = CLKMGR_PERPLL_EN;
plat->bitmask = CLKMGR_PERPLLGRP_EN_USBCLK_MASK;
break;
case AGILEX_SPI_M_CLK:
plat->pllgrp = CLKMGR_PERPLL_EN;
plat->bitmask = CLKMGR_PERPLLGRP_EN_SPIMCLK_MASK;
break;
case AGILEX_NAND_CLK:
plat->pllgrp = CLKMGR_PERPLL_EN;
plat->bitmask = CLKMGR_PERPLLGRP_EN_NANDCLK_MASK;
break;
default:
return -ENXIO;
}

return 0;
}

static int socfpga_clk_enable(struct clk *clk)
{
struct socfpga_clk_plat *plat = dev_get_plat(clk->dev);
uintptr_t base_addr = (uintptr_t)plat->regs;
int ret;

ret = bitmask_from_clk_id(clk);
if (ret)
return ret;

setbits_le32(base_addr + plat->pllgrp, plat->bitmask);

return 0;
}

static int socfpga_clk_disable(struct clk *clk)
{
struct socfpga_clk_plat *plat = dev_get_plat(clk->dev);
uintptr_t base_addr = (uintptr_t)plat->regs;
int ret;

ret = bitmask_from_clk_id(clk);
if (ret)
return ret;

clrbits_le32(base_addr + plat->pllgrp, plat->bitmask);

return 0;
}

Expand Down Expand Up @@ -672,6 +791,7 @@ static int socfpga_clk_of_to_plat(struct udevice *dev)

static struct clk_ops socfpga_clk_ops = {
.enable = socfpga_clk_enable,
.disable = socfpga_clk_disable,
.get_rate = socfpga_clk_get_rate,
};

Expand Down
19 changes: 19 additions & 0 deletions drivers/clk/altera/clk-agilex.h
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Original file line number Diff line number Diff line change
Expand Up @@ -210,7 +210,26 @@ struct cm_config {

#define CLKMGR_LOSTLOCK_SET_MASK BIT(0)

#define CLKMGR_MAINPLLGRP_EN_MPUCLK_MASK BIT(0)
#define CLKMGR_MAINPLLGRP_EN_L4MAINCLK_MASK BIT(1)
#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK BIT(2)
#define CLKMGR_MAINPLLGRP_EN_L4SPCLK_MASK BIT(3)
#define CLKMGR_MAINPLLGRP_EN_CSCLK_MASK BIT(4)
#define CLKMGR_MAINPLLGRP_EN_CSTIMERCLK_MASK BIT(5)
#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK BIT(6)

#define CLKMGR_PERPLLGRP_EN_EMAC0CLK_MASK BIT(0)
#define CLKMGR_PERPLLGRP_EN_EMAC1CLK_MASK BIT(1)
#define CLKMGR_PERPLLGRP_EN_EMAC2CLK_MASK BIT(2)
#define CLKMGR_PERPLLGRP_EN_EMACPTPCLK_MASK BIT(3)
#define CLKMGR_PERPLLGRP_EN_GPIODBCLK_MASK BIT(4)
#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK BIT(5)
#define CLKMGR_PERPLLGRP_EN_S2FUSER1CLK_MASK BIT(6)
#define CLKMGR_PERPLLGRP_EN_PSIREFCLK_MASK BIT(7)
#define CLKMGR_PERPLLGRP_EN_USBCLK_MASK BIT(8)
#define CLKMGR_PERPLLGRP_EN_SPIMCLK_MASK BIT(9)
#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK BIT(10)

#define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET 26
#define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK BIT(26)
#define CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET 27
Expand Down
35 changes: 18 additions & 17 deletions drivers/mmc/socfpga_dw_mmc.c
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2013 Altera Corporation <www.altera.com>
* (C) Copyright 2013-2025 Altera Corporation <www.altera.com>
*/

#include <log.h>
Expand Down Expand Up @@ -29,7 +29,9 @@ struct socfpga_dwmci_plat {

/* socfpga implmentation specific driver private data */
struct dwmci_socfpga_priv_data {
struct udevice *dev;
struct dwmci_host host;
struct clk mmc_clk_ciu;
unsigned int drvsel;
unsigned int smplsel;
};
Expand All @@ -51,28 +53,23 @@ static void socfpga_dwmci_reset(struct udevice *dev)
static int socfpga_dwmci_clksel(struct dwmci_host *host)
{
struct dwmci_socfpga_priv_data *priv = host->priv;
int ret;

u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);

/* Get clock manager base address */
struct udevice *clkmgr_dev;
int ret = uclass_get_device_by_name(UCLASS_CLK, "clock-controller@ffd10000", &clkmgr_dev);

ret = clk_get_by_name(priv->dev, "ciu", &priv->mmc_clk_ciu);
if (ret) {
printf("Failed to get clkmgr device: %d\n", ret);
debug("%s: Failed to get SDMMC clock from dts\n", __func__);
return ret;
}

fdt_addr_t clkmgr_base = dev_read_addr(clkmgr_dev);

if (clkmgr_base == FDT_ADDR_T_NONE) {
printf("Failed to read base address from clkmgr DT node\n");
return -EINVAL;
}

/* Disable SDMMC clock. */
clrbits_le32(clkmgr_base + CLKMGR_PERPLL_EN,
CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
ret = clk_disable(&priv->mmc_clk_ciu);
if (ret) {
printf("%s: Failed to disable SDMMC clock\n", __func__);
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@tienfong tienfong Aug 18, 2025 •
edited
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Prefer dev_err(dev, ...) / dev_dbg(dev, ...) over bare printf() for driver-model devices. It keeps logs consistent and can be filtered per device.

printf()

Global: Always prints unconditionally to the console (UART or log).

No context: Doesn’t automatically include which device/driver emitted the message.

No log level: It’s treated like a raw string — you can’t filter or categorize it.

Legacy: Older code uses printf(), but driver-model code is expected to use dev_*() helpers.

dev_err(dev, ...) / dev_dbg(dev, ...)

Device-aware logging:
These helpers automatically prefix messages with the device’s name/driver instance (e.g. mmc@ff808000: error: clock not found). This makes logs much clearer when you have multiple instances of the same IP (say, multiple MMC controllers).

Log levels:

dev_err(dev, ...) → error log, always shown.

dev_warn(dev, ...) → warning.

dev_info(dev, ...) → informational.

dev_dbg(dev, ...) → debug, compiled in only if DEBUG or CONFIG_DEBUG_DEVRES (depending on subsystem) is enabled. This way you don’t flood normal builds with debug spam.

Integration with log framework:
U-Boot has a log command and runtime loglevel filtering. Messages from dev_*() follow that framework. With printf() you lose that.

Consistency:
Maintainers prefer dev_*() in new DM-based drivers because it keeps all output structured and filterable.

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i see some sections of the code not touched by this patch series still using printf, example - https://github.com/u-boot/u-boot/blame/dca578a9c9decb85271665de8086b8f41731d388/drivers/mmc/socfpga_dw_mmc.c#L84, and https://github.com/u-boot/u-boot/blame/dca578a9c9decb85271665de8086b8f41731d388/drivers/mmc/socfpga_dw_mmc.c#L120.

do you want me to update these as well?

return ret;
}

debug("%s: drvsel %d smplsel %d\n", __func__,
priv->drvsel, priv->smplsel);
Expand All @@ -92,8 +89,11 @@ static int socfpga_dwmci_clksel(struct dwmci_host *host)
#endif

/* Enable SDMMC clock */
setbits_le32(clkmgr_base + CLKMGR_PERPLL_EN,
CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
ret = clk_enable(&priv->mmc_clk_ciu);
if (ret) {
printf("%s: Failed to enable SDMMC clock\n", __func__);
return ret;
}

return 0;
}
Expand Down Expand Up @@ -169,6 +169,7 @@ static int socfpga_dwmmc_probe(struct udevice *dev)
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
struct dwmci_host *host = &priv->host;
priv->dev = dev;
int ret;

ret = socfpga_dwmmc_get_clk_rate(dev);
Expand Down
71 changes: 71 additions & 0 deletions include/dt-bindings/clock/agilex-clock.h
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Original file line number Diff line number Diff line change
@@ -0,0 +1,71 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019, Intel Corporation
*/

#ifndef __AGILEX_CLOCK_H
#define __AGILEX_CLOCK_H

/* fixed rate clocks */
#define AGILEX_OSC1 0
#define AGILEX_CB_INTOSC_HS_DIV2_CLK 1
#define AGILEX_CB_INTOSC_LS_CLK 2
#define AGILEX_L4_SYS_FREE_CLK 3
#define AGILEX_F2S_FREE_CLK 4

/* PLL clocks */
#define AGILEX_MAIN_PLL_CLK 5
#define AGILEX_MAIN_PLL_C0_CLK 6
#define AGILEX_MAIN_PLL_C1_CLK 7
#define AGILEX_MAIN_PLL_C2_CLK 8
#define AGILEX_MAIN_PLL_C3_CLK 9
#define AGILEX_PERIPH_PLL_CLK 10
#define AGILEX_PERIPH_PLL_C0_CLK 11
#define AGILEX_PERIPH_PLL_C1_CLK 12
#define AGILEX_PERIPH_PLL_C2_CLK 13
#define AGILEX_PERIPH_PLL_C3_CLK 14
#define AGILEX_MPU_FREE_CLK 15
#define AGILEX_MPU_CCU_CLK 16
#define AGILEX_BOOT_CLK 17

/* fixed factor clocks */
#define AGILEX_L3_MAIN_FREE_CLK 18
#define AGILEX_NOC_FREE_CLK 19
#define AGILEX_S2F_USR0_CLK 20
#define AGILEX_NOC_CLK 21
#define AGILEX_EMAC_A_FREE_CLK 22
#define AGILEX_EMAC_B_FREE_CLK 23
#define AGILEX_EMAC_PTP_FREE_CLK 24
#define AGILEX_GPIO_DB_FREE_CLK 25
#define AGILEX_SDMMC_FREE_CLK 26
#define AGILEX_S2F_USER0_FREE_CLK 27
#define AGILEX_S2F_USER1_FREE_CLK 28
#define AGILEX_PSI_REF_FREE_CLK 29

/* Gate clocks */
#define AGILEX_MPU_CLK 30
#define AGILEX_MPU_PERIPH_CLK 31
#define AGILEX_L4_MAIN_CLK 32
#define AGILEX_L4_MP_CLK 33
#define AGILEX_L4_SP_CLK 34
#define AGILEX_CS_AT_CLK 35
#define AGILEX_CS_TRACE_CLK 36
#define AGILEX_CS_PDBG_CLK 37
#define AGILEX_CS_TIMER_CLK 38
#define AGILEX_S2F_USER0_CLK 39
#define AGILEX_EMAC0_CLK 40
#define AGILEX_EMAC1_CLK 41
#define AGILEX_EMAC2_CLK 42
#define AGILEX_EMAC_PTP_CLK 43
#define AGILEX_GPIO_DB_CLK 44
#define AGILEX_NAND_CLK 45
#define AGILEX_PSI_REF_CLK 46
#define AGILEX_S2F_USER1_CLK 47
#define AGILEX_SDMMC_CLK 48
#define AGILEX_SPI_M_CLK 49
#define AGILEX_USB_CLK 50
#define AGILEX_NAND_X_CLK 51
#define AGILEX_NAND_ECC_CLK 52
#define AGILEX_NUM_CLKS 53

#endif /* __AGILEX_CLOCK_H */