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Commits on Jul 28, 2018

• Correct bad README.md hdl-tools/scripts link

  

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Commits on Mar 15, 2018

• Properly apply Apache v2 License

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Commits on Jun 5, 2017

• Use ibm/hdl-tools over old seldridge/hdl-scripts

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Commits on Apr 2, 2017

• Re-license as Apache v2, chmods, utf-8

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Commits on Dec 17, 2015

• Add CORDIC circular and hyperbolic units

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Commits on Nov 11, 2015

• Merge branch 'master' of github.com:seldridge/verilog

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• Make ram_infer UNIX-friendly

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Commits on Jun 19, 2015

• Update hdl-scripts reference

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Commits on May 21, 2015

• Update hdl-scripts submodule ref

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Commits on May 12, 2015

• Updated README.md with hdl-scripts info

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• Add hdl-scripts submodule

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Commits on May 5, 2015

• Remove '0 SystemVerilog Syntax from sqrt_generic

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• Reorder sqrt_generic reset for synthesis

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Commits on Apr 24, 2015

• Update README.md

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• Convert sqrt_generic to Verilog 2001 Syntax

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Commits on Apr 23, 2015

• Add rst_n condition, minor comment updates

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• Directory cleanup of sqrt_generic

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• Add GPLv3 to sqrt_generic.v and t_sqrt_generic.v

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• Merge branch 'master' of github.com:seldridge/verilog

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• Refactor sqrt_pipelined to sqrt_generic

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Commits on Apr 3, 2015

• Update README.md

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• Update verilog_math copyright date

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• Merge branch 'master' of github.com:seldridge/verilog

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• Add fixed point to real conversion

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• Add (largely untested) div_pipelined.v

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Commits on Feb 7, 2015

• Eye centering of uart_rx and bug fix for tx

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• Fix `PACK bug due to named generate block

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Commits on Feb 3, 2015

• Merge branch 'master' of github.com:seldridge/verilog

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• verilog_math.vh genvar fixes

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• mv testbench to sim directory

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• Updated README.md

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• Merge branch 'master' of github.com:seldridge/verilog

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• Added UART TX and RX modules

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Commits on Apr 20, 2014

• Modified pipeline_registers added with "set"

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Commits on Dec 11, 2013

• Additional random function added to verilog_math

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