Modern designs for embedded many-core systems increasingly include application-specific units to ... more Modern designs for embedded many-core systems increasingly include application-specific units to accelerate key computational kernels with orders-of-magnitude higher execution speed and energy efficiency compared to software counterparts. A promising architectural template is based on heterogeneous clusters, where simple RISC cores and specialized HW units (HWPU) communicate in a tightly-coupled manner via L1 shared memory. Efficiently integrating processors and a high number of HW Processing Units (HWPUs) in such an system poses two main challenges, namely, architectural scalability and programmability. In this paper we describe an optimized Data Pump (DP) which connects several accelerators to a restricted set of communication ports, and acts as a virtualization layer for programming, exposing FIFO queues to offload “HW tasks” to them through a set of lightweight APIs. In this work, we aim at optimizing both these mechanisms, for respectively reducing modules area and making progr...
This paper is concerned with solar driven sensors deployed in an outdoor environment. We present ... more This paper is concerned with solar driven sensors deployed in an outdoor environment. We present feedback controllers which adapt parameters of the application such that a max- imal utility is obtained while respecting the time-varying amount of available energy. We show that already simple applications lead to complex optimization problems, involv- ing unacceptable running times and energy consumptions for resource
The paper studies the case of a sensor node which is operating with the power generated by an env... more The paper studies the case of a sensor node which is operating with the power generated by an environmental source. We present our model of an energy driven scheduling scenario that is characterized by the capacity of the node{\^{a}}€™s energy storage, the deadlines and the power dissipation of the tasks to be performed. Since the execution of these tasks requires
, Energy harvesting has recently emerged as a feasible option to increase the operating time of s... more , Energy harvesting has recently emerged as a feasible option to increase the operating time of sensor networks. If each node, of the network, however, is powered by a fluctuating energy source, common power management solutions have to be reconceived., This holds in particular if real-time responsiveness of a given application has to be guaranteed. Task scheduling at the
Solar harvesting circuits have been recently proposed to in- crease the autonomy of embedded syst... more Solar harvesting circuits have been recently proposed to in- crease the autonomy of embedded systems. One key design chal- lenge is how to optimize the efficiency of solar energy collection under non stationary light conditions. This paper proposes a sca- venger that exploits miniaturized photovoltaic modules to perform automatic maximum power point tracking at a minimum energy cost. The system
Recently, there has been a substantial interest in the de- sign of systems that receive their ene... more Recently, there has been a substantial interest in the de- sign of systems that receive their energy from regenerative sources such as solar cells. In contrast to approaches that attempt to minimize the power consumption we are con- cerned with adapting parameters of the application such that a maximal utility is obtained while respecting the lim- ited and time-varying amount
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers, 2006
An 8 times 16 array of sensing micro-sites employs a fully-electrical label-free technique for DN... more An 8 times 16 array of sensing micro-sites employs a fully-electrical label-free technique for DNA recognition using capacitance measurement and is fabricated in 0.5mum CMOS with added noble metal. Repeatability and parallel detection capability have been demonstrated. The DNA-chip is suitable for low-cost, fully-integrated point-of-care applications
P2012 is an area- and power-efficient many-core computing fabric based on multiple globally async... more P2012 is an area- and power-efficient many-core computing fabric based on multiple globally asynchronous, locally synchronous (GALS) clusters supporting aggressive fine-grained power, reliability and variability management. Clusters feature up to 16 processors and one control processor with independent instruction streams sharing a multi-banked L1 data memory, a multi-channel DMA engine, and specialized hardware for synchronization and scheduling. P2012 achieves extreme
Proceedings of 1996 International Symposium on Low Power Electronics and Design, 1996
The presence of large current peaks on the power and ground lines is a serious concern for design... more The presence of large current peaks on the power and ground lines is a serious concern for designers of synchronous digital circuits. Current peaks are caused by the simultaneous switching of highly loaded clock lines and by the signal propagation through the sequential logic elements. In this work we propose a methodology for reducing the amplitude of the current peaks. This result is obtained by clock skew optimization. We propose an algorithm that, for a given clock cycle time, determines the clock arrival time at each flip-flop in order to minimize the current peaks while respecting timing constraint. Our results on benchmark circuits show that current peaks can be reduced without penalty on cycle time and average power dissipation. Our methodology is therefore well-suited for low-power systems with reduced supply voltage, where low noise margins are a primary concern. . His research interests are in synthesis and simulation techniques for low-power systems. He is also interested in logic synthesis, behavioral synthesis and design for testability. Mr. Benini received an M.S. degree in 1994 in electrical engineering from Stanford University, and a Laurea degree (summa cum laude) in 1991 from University of Bologna. He is a student member of the IEEE.
Proceedings International Conference on Computer Design. VLSI in Computers and Processors, 1996
... New tool usage paradi,gns may emerge: users could temporarily connect to a tool provider, per... more ... New tool usage paradi,gns may emerge: users could temporarily connect to a tool provider, perform a specific task and be billed on a usage-time basis. ... For applications where higher interactivity is required, we provide a novel paradi,gm called interactive remote ex-ecution. ...
Reliable DNA detection is of great importance for the development of the Lab-on-chip technology. ... more Reliable DNA detection is of great importance for the development of the Lab-on-chip technology. The effort of the most recent projects on this field is to integrate all necessary operations, such as sample preparation (mixing, PCR amplification) together with the sensor user for DNA detection. Among the different ways to sense the DNA hybridization, fluorescence based detection has been favored
Proceedings of the 2001 international symposium on Low power electronics and design - ISLPED '01, 2001
This paper contributes a novel approach for reducing static code size and instruction fetch energ... more This paper contributes a novel approach for reducing static code size and instruction fetch energy for cache-based core processors running embedded applications. Our implementation of the decompression unit guarantees fast and low-energy, on-the-fly instruction decompression at each cache lookup. The decompressor is placed outside the core boundaries; therefore, processor architecture does not need any modification, making the proposed compression approach
In deep submicron designs of Multiprocessor Systems-on-Chip (MPSoC) architectures, uncompensated ... more In deep submicron designs of Multiprocessor Systems-on-Chip (MPSoC) architectures, uncompensated within-die process variations and aging effects will lead to an increasing uncertainty and unbalancing of expected core lifetimes. In this paper we present an adaptive workload allocation strategy for run-time compensation of variations- and aging-induced unbalanced core lifetimes by means of core activity duty cycling. The proposed techniques regulates the
In this work we study the problem of estimating the power dissipation of the atomic components (m... more In this work we study the problem of estimating the power dissipation of the atomic components (macros) used to implement basic operations in behavioral synthesis. We first precisely define the key requisites for behavioral power macro-models and we briefly evaluate the suitability of several approaches proposed in the past. We then focus on a specific macro-modeling methodology that appears to
Abstract The impact of variability on sub-45nm CMOS multimedia platforms makes hard to provide ap... more Abstract The impact of variability on sub-45nm CMOS multimedia platforms makes hard to provide application QoS guarantees, as the speed variations across the cores may cause sub-optimal and sample-dependent utilization of the available resources and energy budget. These effects can be compensated by an efficient allocation of the workload at run-time. In the context of multimedia applications, a critical objective is to compensate core speed variability while matching time constraints without impacting the energy ...
Modern designs for embedded many-core systems increasingly include application-specific units to ... more Modern designs for embedded many-core systems increasingly include application-specific units to accelerate key computational kernels with orders-of-magnitude higher execution speed and energy efficiency compared to software counterparts. A promising architectural template is based on heterogeneous clusters, where simple RISC cores and specialized HW units (HWPU) communicate in a tightly-coupled manner via L1 shared memory. Efficiently integrating processors and a high number of HW Processing Units (HWPUs) in such an system poses two main challenges, namely, architectural scalability and programmability. In this paper we describe an optimized Data Pump (DP) which connects several accelerators to a restricted set of communication ports, and acts as a virtualization layer for programming, exposing FIFO queues to offload “HW tasks” to them through a set of lightweight APIs. In this work, we aim at optimizing both these mechanisms, for respectively reducing modules area and making progr...
This paper is concerned with solar driven sensors deployed in an outdoor environment. We present ... more This paper is concerned with solar driven sensors deployed in an outdoor environment. We present feedback controllers which adapt parameters of the application such that a max- imal utility is obtained while respecting the time-varying amount of available energy. We show that already simple applications lead to complex optimization problems, involv- ing unacceptable running times and energy consumptions for resource
The paper studies the case of a sensor node which is operating with the power generated by an env... more The paper studies the case of a sensor node which is operating with the power generated by an environmental source. We present our model of an energy driven scheduling scenario that is characterized by the capacity of the node{\^{a}}€™s energy storage, the deadlines and the power dissipation of the tasks to be performed. Since the execution of these tasks requires
, Energy harvesting has recently emerged as a feasible option to increase the operating time of s... more , Energy harvesting has recently emerged as a feasible option to increase the operating time of sensor networks. If each node, of the network, however, is powered by a fluctuating energy source, common power management solutions have to be reconceived., This holds in particular if real-time responsiveness of a given application has to be guaranteed. Task scheduling at the
Solar harvesting circuits have been recently proposed to in- crease the autonomy of embedded syst... more Solar harvesting circuits have been recently proposed to in- crease the autonomy of embedded systems. One key design chal- lenge is how to optimize the efficiency of solar energy collection under non stationary light conditions. This paper proposes a sca- venger that exploits miniaturized photovoltaic modules to perform automatic maximum power point tracking at a minimum energy cost. The system
Recently, there has been a substantial interest in the de- sign of systems that receive their ene... more Recently, there has been a substantial interest in the de- sign of systems that receive their energy from regenerative sources such as solar cells. In contrast to approaches that attempt to minimize the power consumption we are con- cerned with adapting parameters of the application such that a maximal utility is obtained while respecting the lim- ited and time-varying amount
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers, 2006
An 8 times 16 array of sensing micro-sites employs a fully-electrical label-free technique for DN... more An 8 times 16 array of sensing micro-sites employs a fully-electrical label-free technique for DNA recognition using capacitance measurement and is fabricated in 0.5mum CMOS with added noble metal. Repeatability and parallel detection capability have been demonstrated. The DNA-chip is suitable for low-cost, fully-integrated point-of-care applications
P2012 is an area- and power-efficient many-core computing fabric based on multiple globally async... more P2012 is an area- and power-efficient many-core computing fabric based on multiple globally asynchronous, locally synchronous (GALS) clusters supporting aggressive fine-grained power, reliability and variability management. Clusters feature up to 16 processors and one control processor with independent instruction streams sharing a multi-banked L1 data memory, a multi-channel DMA engine, and specialized hardware for synchronization and scheduling. P2012 achieves extreme
Proceedings of 1996 International Symposium on Low Power Electronics and Design, 1996
The presence of large current peaks on the power and ground lines is a serious concern for design... more The presence of large current peaks on the power and ground lines is a serious concern for designers of synchronous digital circuits. Current peaks are caused by the simultaneous switching of highly loaded clock lines and by the signal propagation through the sequential logic elements. In this work we propose a methodology for reducing the amplitude of the current peaks. This result is obtained by clock skew optimization. We propose an algorithm that, for a given clock cycle time, determines the clock arrival time at each flip-flop in order to minimize the current peaks while respecting timing constraint. Our results on benchmark circuits show that current peaks can be reduced without penalty on cycle time and average power dissipation. Our methodology is therefore well-suited for low-power systems with reduced supply voltage, where low noise margins are a primary concern. . His research interests are in synthesis and simulation techniques for low-power systems. He is also interested in logic synthesis, behavioral synthesis and design for testability. Mr. Benini received an M.S. degree in 1994 in electrical engineering from Stanford University, and a Laurea degree (summa cum laude) in 1991 from University of Bologna. He is a student member of the IEEE.
Proceedings International Conference on Computer Design. VLSI in Computers and Processors, 1996
... New tool usage paradi,gns may emerge: users could temporarily connect to a tool provider, per... more ... New tool usage paradi,gns may emerge: users could temporarily connect to a tool provider, perform a specific task and be billed on a usage-time basis. ... For applications where higher interactivity is required, we provide a novel paradi,gm called interactive remote ex-ecution. ...
Reliable DNA detection is of great importance for the development of the Lab-on-chip technology. ... more Reliable DNA detection is of great importance for the development of the Lab-on-chip technology. The effort of the most recent projects on this field is to integrate all necessary operations, such as sample preparation (mixing, PCR amplification) together with the sensor user for DNA detection. Among the different ways to sense the DNA hybridization, fluorescence based detection has been favored
Proceedings of the 2001 international symposium on Low power electronics and design - ISLPED '01, 2001
This paper contributes a novel approach for reducing static code size and instruction fetch energ... more This paper contributes a novel approach for reducing static code size and instruction fetch energy for cache-based core processors running embedded applications. Our implementation of the decompression unit guarantees fast and low-energy, on-the-fly instruction decompression at each cache lookup. The decompressor is placed outside the core boundaries; therefore, processor architecture does not need any modification, making the proposed compression approach
In deep submicron designs of Multiprocessor Systems-on-Chip (MPSoC) architectures, uncompensated ... more In deep submicron designs of Multiprocessor Systems-on-Chip (MPSoC) architectures, uncompensated within-die process variations and aging effects will lead to an increasing uncertainty and unbalancing of expected core lifetimes. In this paper we present an adaptive workload allocation strategy for run-time compensation of variations- and aging-induced unbalanced core lifetimes by means of core activity duty cycling. The proposed techniques regulates the
In this work we study the problem of estimating the power dissipation of the atomic components (m... more In this work we study the problem of estimating the power dissipation of the atomic components (macros) used to implement basic operations in behavioral synthesis. We first precisely define the key requisites for behavioral power macro-models and we briefly evaluate the suitability of several approaches proposed in the past. We then focus on a specific macro-modeling methodology that appears to
Abstract The impact of variability on sub-45nm CMOS multimedia platforms makes hard to provide ap... more Abstract The impact of variability on sub-45nm CMOS multimedia platforms makes hard to provide application QoS guarantees, as the speed variations across the cores may cause sub-optimal and sample-dependent utilization of the available resources and energy budget. These effects can be compensated by an efficient allocation of the workload at run-time. In the context of multimedia applications, a critical objective is to compensate core speed variability while matching time constraints without impacting the energy ...
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Papers by Luca Benini