2011 IEEE Eighth International Conference on Mobile Ad-Hoc and Sensor Systems, 2011
... Darko Petrovic and Riad Kanan University of Applied Sciences in Sion Rte du Rawyl 47, 1950 Si... more ... Darko Petrovic and Riad Kanan University of Applied Sciences in Sion Rte du Rawyl 47, 1950 Sion, Switzerland darko.petrovic@hevs.ch, riad.kanan@hevs.ch ... The average power consumption of a sensor node when active is roughly in the range of twenty milli-watts. ...
Proceedinbgs of the 24th ACM symposium on Parallelism in algorithms and architectures - SPAA '12, 2012
Many-core chips with more than 1000 cores are expected by the end of the decade. To overcome scal... more Many-core chips with more than 1000 cores are expected by the end of the decade. To overcome scalability issues related to cache coherence at such a scale, one of the main research directions is to leverage the message-passing programming model. The Intel Single-Chip Cloud Computer (SCC) is a prototype of a message-passing many-core chip. It offers the ability to move data between on-chip Message Passing Buffers (MPB) using Remote Memory Access (RMA). Performance of message-passing applications is directly affected by efficiency of collective operations, such as broadcast. In this paper, we study how to make use of the MPBs to implement an efficient broadcast algorithm for the SCC. We propose OC-Bcast (On-Chip Broadcast), a pipelined k-ary tree algorithm tailored to exploit the parallelism provided by on-chip RMA. Using a LogP-based model, we present an analytical evaluation that compares our algorithm with the state-of-the-art broadcast algorithms implemented for the SCC. As predicted by the model, experimental results show that OC-Bcast attains almost three times better throughput, and improves latency by at least 27%. Furthermore, the analytical evaluation highlights the benefits of our approach: OC-Bcast takes direct advantage of RMA, unlike the other considered broadcast algorithms, which are based on a higher-level send/receive interface. This leads us to the conclusion that RMA-based collective operations are needed to take full advantage of hardware features of future message-passing many-core architectures.
As the level of parallelism in manycore processors keeps increasing, providing efficient mechanis... more As the level of parallelism in manycore processors keeps increasing, providing efficient mechanisms for thread synchronization in concurrent programs is becoming a major concern. On cache-coherent shared-memory processors, synchronization efficiency is ultimately limited by the performance of the underlying cache coherence protocol. This paper studies how hardware support for message passing can improve synchronization performance. Considering the ubiquitous problem of mutual exclusion, we adapt two stateof-the-art solutions used on shared-memory processors, namely the server approach and the combining approach, to leverage the potential of hardware message passing. We propose HYBCOMB, a novel combining algorithm that uses both message passing and shared memory features of emerging hybrid processors. We also introduce MP-SERVER, a straightforward adaptation of the server approach to hardware message passing. Evaluation on Tilera's TILE-Gx processor shows that MP-SERVER can execute contended critical sections with unprecedented throughput, as stalls related to cache coherence are removed from the critical path. HYB-COMB can achieve comparable performance, while avoiding the need to dedicate server cores. Consequently, our queue and stack implementations, based on MP-SERVER and HYB-COMB, largely outperform their most efficient pure-sharedmemory counterparts.
2012 IEEE 26th International Conference on Advanced Information Networking and Applications, 2012
Virtual machine (VM) replication has been recognized as an inexpensive way of providing high avai... more Virtual machine (VM) replication has been recognized as an inexpensive way of providing high availability on commodity hardware. Unfortunately, its impact on system performance is far from negligible and strategies have been proposed to mitigate this problem. In this paper we take a look at VM replication from a different perspective: the choice of a hyper visor. Namely, the differences
Aim To examine levels of fine particulates of secondhand smoke (SHS) in outdoor dining/smoking ar... more Aim To examine levels of fine particulates of secondhand smoke (SHS) in outdoor dining/smoking areas and the adjacent indoor dining areas of restaurants to assess possible drift via open windows/doors.
Đakonese -pomagale su svećenicima u skrbi za bolesne i siromašne. Išle su u kuće i u košarama nos... more Đakonese -pomagale su svećenicima u skrbi za bolesne i siromašne. Išle su u kuće i u košarama nosile hranu i lijekove -to danas nazivamo preteče torbe patronažne sestre. Njegom su se bavili i muškarci i žene -svatko je brinuo o svom spolu. Phoebe je bila prva đakonesa. Za oboljele je skrbio i red udovica, nisu nužno bile udovice i Virginski red, osnovan 400 g. u Kostantinopolisu, radile su pod nadzorom Olimpije, a ona je postala udovica sa 19g. i ostatak života posvetila je radu s bolesnima i siromašnima. Bila je izniman organizator i pod njenim je nadzorom radilo 40 đakonesa. Olimpija je živjela asketskim životom.
2011 IEEE Eighth International Conference on Mobile Ad-Hoc and Sensor Systems, 2011
... Darko Petrovic and Riad Kanan University of Applied Sciences in Sion Rte du Rawyl 47, 1950 Si... more ... Darko Petrovic and Riad Kanan University of Applied Sciences in Sion Rte du Rawyl 47, 1950 Sion, Switzerland darko.petrovic@hevs.ch, riad.kanan@hevs.ch ... The average power consumption of a sensor node when active is roughly in the range of twenty milli-watts. ...
Proceedinbgs of the 24th ACM symposium on Parallelism in algorithms and architectures - SPAA '12, 2012
Many-core chips with more than 1000 cores are expected by the end of the decade. To overcome scal... more Many-core chips with more than 1000 cores are expected by the end of the decade. To overcome scalability issues related to cache coherence at such a scale, one of the main research directions is to leverage the message-passing programming model. The Intel Single-Chip Cloud Computer (SCC) is a prototype of a message-passing many-core chip. It offers the ability to move data between on-chip Message Passing Buffers (MPB) using Remote Memory Access (RMA). Performance of message-passing applications is directly affected by efficiency of collective operations, such as broadcast. In this paper, we study how to make use of the MPBs to implement an efficient broadcast algorithm for the SCC. We propose OC-Bcast (On-Chip Broadcast), a pipelined k-ary tree algorithm tailored to exploit the parallelism provided by on-chip RMA. Using a LogP-based model, we present an analytical evaluation that compares our algorithm with the state-of-the-art broadcast algorithms implemented for the SCC. As predicted by the model, experimental results show that OC-Bcast attains almost three times better throughput, and improves latency by at least 27%. Furthermore, the analytical evaluation highlights the benefits of our approach: OC-Bcast takes direct advantage of RMA, unlike the other considered broadcast algorithms, which are based on a higher-level send/receive interface. This leads us to the conclusion that RMA-based collective operations are needed to take full advantage of hardware features of future message-passing many-core architectures.
As the level of parallelism in manycore processors keeps increasing, providing efficient mechanis... more As the level of parallelism in manycore processors keeps increasing, providing efficient mechanisms for thread synchronization in concurrent programs is becoming a major concern. On cache-coherent shared-memory processors, synchronization efficiency is ultimately limited by the performance of the underlying cache coherence protocol. This paper studies how hardware support for message passing can improve synchronization performance. Considering the ubiquitous problem of mutual exclusion, we adapt two stateof-the-art solutions used on shared-memory processors, namely the server approach and the combining approach, to leverage the potential of hardware message passing. We propose HYBCOMB, a novel combining algorithm that uses both message passing and shared memory features of emerging hybrid processors. We also introduce MP-SERVER, a straightforward adaptation of the server approach to hardware message passing. Evaluation on Tilera's TILE-Gx processor shows that MP-SERVER can execute contended critical sections with unprecedented throughput, as stalls related to cache coherence are removed from the critical path. HYB-COMB can achieve comparable performance, while avoiding the need to dedicate server cores. Consequently, our queue and stack implementations, based on MP-SERVER and HYB-COMB, largely outperform their most efficient pure-sharedmemory counterparts.
2012 IEEE 26th International Conference on Advanced Information Networking and Applications, 2012
Virtual machine (VM) replication has been recognized as an inexpensive way of providing high avai... more Virtual machine (VM) replication has been recognized as an inexpensive way of providing high availability on commodity hardware. Unfortunately, its impact on system performance is far from negligible and strategies have been proposed to mitigate this problem. In this paper we take a look at VM replication from a different perspective: the choice of a hyper visor. Namely, the differences
Aim To examine levels of fine particulates of secondhand smoke (SHS) in outdoor dining/smoking ar... more Aim To examine levels of fine particulates of secondhand smoke (SHS) in outdoor dining/smoking areas and the adjacent indoor dining areas of restaurants to assess possible drift via open windows/doors.
Đakonese -pomagale su svećenicima u skrbi za bolesne i siromašne. Išle su u kuće i u košarama nos... more Đakonese -pomagale su svećenicima u skrbi za bolesne i siromašne. Išle su u kuće i u košarama nosile hranu i lijekove -to danas nazivamo preteče torbe patronažne sestre. Njegom su se bavili i muškarci i žene -svatko je brinuo o svom spolu. Phoebe je bila prva đakonesa. Za oboljele je skrbio i red udovica, nisu nužno bile udovice i Virginski red, osnovan 400 g. u Kostantinopolisu, radile su pod nadzorom Olimpije, a ona je postala udovica sa 19g. i ostatak života posvetila je radu s bolesnima i siromašnima. Bila je izniman organizator i pod njenim je nadzorom radilo 40 đakonesa. Olimpija je živjela asketskim životom.
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Papers by Darko Petrović