Seventh IEEE International High-Level Design Validation and Test Workshop, 2002., 2002
We present X-Gen, a model-based test-case generator designed for systems and systems on a chip (S... more We present X-Gen, a model-based test-case generator designed for systems and systems on a chip (SoCs). X-Gen provides a framework and a set of building blocks for system-level test-case generation. At the core of this framework lies a system model, which consists of component types, their configuration, and the interactions between them. Building blocks include commonly used concepts such as memories, registers, and address translation mechanisms. Once a system is modeled, X-Gen provides a rich language for describing test cases. Through this language, users can specify requests that cover the full spectrum between highly directed tests to completely random ones. X-Gen is currently in preliminary use at IBM for the verification of two different designs-a high-end multi-processor server and a state-of-the-art SoC.
ABSTRACT We propose a framework for the creation and maintenance of multicast trees in hierarchic... more ABSTRACT We propose a framework for the creation and maintenance of multicast trees in hierarchical ATM networks. This framework aims at coping with an inherent difficulty of topology aggregation in such networks. The main idea of the proposed framework is to distribute the tree topology information among a set of hierarchical multicast group servers (MGS) nominated for each multicast tree, while keeping regions that do not have a member in the multicast group unaware of the tree. The framework can be employed with every multicast routing algorithm designed for non-hierarchical networks
This paper reports on the verification models of twelve systems including servers and advanced pr... more This paper reports on the verification models of twelve systems including servers and advanced processors. We focus on system-level stimuli generation and study reuse in subsequent system models.
Functional verification of systems is aimed at validating the integration of previously verified ... more Functional verification of systems is aimed at validating the integration of previously verified components. It deals with complex designs, and invariably suffers from scarce resources. We present a set of methods, collectively known as testing knowledge, aimed at increasing the quality of automatically generated system-level test-cases. Testing knowledge reduces the time and effort required to achieve high coverage of the verified design.
Multimedia SoCs are characterized by a main controller that directs the activity of several cores... more Multimedia SoCs are characterized by a main controller that directs the activity of several cores, each of which is in charge of a stage in the processing of a media stream. The verification of these SoCs is a significant challenge due to time-to-market constraints and system complexity. We present a novel approach to system-level, random test case generation for multimedia SoCs, and a tool, called SoCVer, that implements this approach. We use the SoC's main controller point of view for controlling the flow of data in the SoC. Test case generation is done by allocating processing tasks to the various cores and determining which core processes which data item at what time. Solving these scheduling problems allows SoCVer to generate software for the SoC's main controller; this software coordinates and synchronizes the operations of all the cores on the chip without the need for the real operational software. We demonstrate the use of SoCVer using a DVD player SoC. Figure 4: 'Play MPEG-2' over an 'IPBB' stream scheduling problem solution
Simulation of automatically-generated test programs is the primary means for verifying complex ha... more Simulation of automatically-generated test programs is the primary means for verifying complex hardware designs and random test program generators therefore play a major role in the verification process of micro-processors. The input for a test program generator is typically an abstract specification-a template-of the tests to be generated. Due to randomness, generators often encounter situations that were not anticipated when the test specification was written. In this paper, we introduce the concept of adaptive test program generation, which is designed to handle these unforeseen situations. We propose a technique that defines unexpected events together with their alternative program specifications. When an event is detected, its corresponding alternative specification is injected into the test program.
We present a methodology for scheduling system-level transactions generated by a test-case genera... more We present a methodology for scheduling system-level transactions generated by a test-case generator. A system, in this context, may be composed of multiple processors, busses, bus-bridges, memories, etc. The methodology is based on an exploration of scheduling abilities in a hardware system. In its focus is a language for specifying transactions and their ordering. Through the use of hierarchy, the language provides the possibility of applying high-level scheduling requests. The methodology is realized in X-Gen, a system-level test-case generator used in IBM. The model and algorithm used by this tool are also discussed.
Functional verification of modern hardware design consumes roughly 70% of the effort invested in ... more Functional verification of modern hardware design consumes roughly 70% of the effort invested in the design cycle. Simulation of randomly generated stimuli is the main means of achieving functional verification. A typical verification effort is centered around a stimuli generator which produces a massive amount of test cases that are simulated on the verified design. Bugs are then identified when the design behaves incorrectly. (in some cases this process is complemented by some amount of formal verification).
We present a new test case generation technology, specifically targeted at verifying systems that... more We present a new test case generation technology, specifically targeted at verifying systems that include address translation mechanisms. The ever-growing demand for performance makes these mechanisms more complex, thereby increasing the risk of bugs and increasing the need for such technology. DeepTrans is a package that provides model-based test generation capabilities to verify translation mechanisms based on a modeling language.
We present X-Gen, a model-based test-case generator designed for systems and systems on a chip (S... more We present X-Gen, a model-based test-case generator designed for systems and systems on a chip (SoCs). X-Gen provides a framework and a set of building blocks for system-level test-case generation. At the core of this framework lies a system model, which consists of component types, their configuration, and the interactions between them. Building blocks include commonly used concepts such as memories, registers, and address translation mechanisms. Once a system is modeled, X-Gen provides a rich language for describing test cases. Through this language, users can specify requests that cover the full spectrum between highly directed tests to completely random ones. X-Gen is currently in preliminary use at IBM for the verification of two different designs-a high-end multi-processor server and a state-of-the-art SoC.
The paper presents a method for generating solutions of a constraint satisfaction problem (CSP) u... more The paper presents a method for generating solutions of a constraint satisfaction problem (CSP) uniformly at random. The main idea is to transform the constraint network into a belief network that expresses a uniform random distribution over its set of solutions and then use known sampling algorithms over belief networks. The motivation for this tasks comes from hardware verification. Random test program generation for hardware verification can be modeled and performed through CSP techniques, and is an application in which uniform random solution sampling is required.
Seventh IEEE International High-Level Design Validation and Test Workshop, 2002., 2002
We present X-Gen, a model-based test-case generator designed for systems and systems on a chip (S... more We present X-Gen, a model-based test-case generator designed for systems and systems on a chip (SoCs). X-Gen provides a framework and a set of building blocks for system-level test-case generation. At the core of this framework lies a system model, which consists of component types, their configuration, and the interactions between them. Building blocks include commonly used concepts such as memories, registers, and address translation mechanisms. Once a system is modeled, X-Gen provides a rich language for describing test cases. Through this language, users can specify requests that cover the full spectrum between highly directed tests to completely random ones. X-Gen is currently in preliminary use at IBM for the verification of two different designs-a high-end multi-processor server and a state-of-the-art SoC.
ABSTRACT We propose a framework for the creation and maintenance of multicast trees in hierarchic... more ABSTRACT We propose a framework for the creation and maintenance of multicast trees in hierarchical ATM networks. This framework aims at coping with an inherent difficulty of topology aggregation in such networks. The main idea of the proposed framework is to distribute the tree topology information among a set of hierarchical multicast group servers (MGS) nominated for each multicast tree, while keeping regions that do not have a member in the multicast group unaware of the tree. The framework can be employed with every multicast routing algorithm designed for non-hierarchical networks
This paper reports on the verification models of twelve systems including servers and advanced pr... more This paper reports on the verification models of twelve systems including servers and advanced processors. We focus on system-level stimuli generation and study reuse in subsequent system models.
Functional verification of systems is aimed at validating the integration of previously verified ... more Functional verification of systems is aimed at validating the integration of previously verified components. It deals with complex designs, and invariably suffers from scarce resources. We present a set of methods, collectively known as testing knowledge, aimed at increasing the quality of automatically generated system-level test-cases. Testing knowledge reduces the time and effort required to achieve high coverage of the verified design.
Multimedia SoCs are characterized by a main controller that directs the activity of several cores... more Multimedia SoCs are characterized by a main controller that directs the activity of several cores, each of which is in charge of a stage in the processing of a media stream. The verification of these SoCs is a significant challenge due to time-to-market constraints and system complexity. We present a novel approach to system-level, random test case generation for multimedia SoCs, and a tool, called SoCVer, that implements this approach. We use the SoC's main controller point of view for controlling the flow of data in the SoC. Test case generation is done by allocating processing tasks to the various cores and determining which core processes which data item at what time. Solving these scheduling problems allows SoCVer to generate software for the SoC's main controller; this software coordinates and synchronizes the operations of all the cores on the chip without the need for the real operational software. We demonstrate the use of SoCVer using a DVD player SoC. Figure 4: 'Play MPEG-2' over an 'IPBB' stream scheduling problem solution
Simulation of automatically-generated test programs is the primary means for verifying complex ha... more Simulation of automatically-generated test programs is the primary means for verifying complex hardware designs and random test program generators therefore play a major role in the verification process of micro-processors. The input for a test program generator is typically an abstract specification-a template-of the tests to be generated. Due to randomness, generators often encounter situations that were not anticipated when the test specification was written. In this paper, we introduce the concept of adaptive test program generation, which is designed to handle these unforeseen situations. We propose a technique that defines unexpected events together with their alternative program specifications. When an event is detected, its corresponding alternative specification is injected into the test program.
We present a methodology for scheduling system-level transactions generated by a test-case genera... more We present a methodology for scheduling system-level transactions generated by a test-case generator. A system, in this context, may be composed of multiple processors, busses, bus-bridges, memories, etc. The methodology is based on an exploration of scheduling abilities in a hardware system. In its focus is a language for specifying transactions and their ordering. Through the use of hierarchy, the language provides the possibility of applying high-level scheduling requests. The methodology is realized in X-Gen, a system-level test-case generator used in IBM. The model and algorithm used by this tool are also discussed.
Functional verification of modern hardware design consumes roughly 70% of the effort invested in ... more Functional verification of modern hardware design consumes roughly 70% of the effort invested in the design cycle. Simulation of randomly generated stimuli is the main means of achieving functional verification. A typical verification effort is centered around a stimuli generator which produces a massive amount of test cases that are simulated on the verified design. Bugs are then identified when the design behaves incorrectly. (in some cases this process is complemented by some amount of formal verification).
We present a new test case generation technology, specifically targeted at verifying systems that... more We present a new test case generation technology, specifically targeted at verifying systems that include address translation mechanisms. The ever-growing demand for performance makes these mechanisms more complex, thereby increasing the risk of bugs and increasing the need for such technology. DeepTrans is a package that provides model-based test generation capabilities to verify translation mechanisms based on a modeling language.
We present X-Gen, a model-based test-case generator designed for systems and systems on a chip (S... more We present X-Gen, a model-based test-case generator designed for systems and systems on a chip (SoCs). X-Gen provides a framework and a set of building blocks for system-level test-case generation. At the core of this framework lies a system model, which consists of component types, their configuration, and the interactions between them. Building blocks include commonly used concepts such as memories, registers, and address translation mechanisms. Once a system is modeled, X-Gen provides a rich language for describing test cases. Through this language, users can specify requests that cover the full spectrum between highly directed tests to completely random ones. X-Gen is currently in preliminary use at IBM for the verification of two different designs-a high-end multi-processor server and a state-of-the-art SoC.
The paper presents a method for generating solutions of a constraint satisfaction problem (CSP) u... more The paper presents a method for generating solutions of a constraint satisfaction problem (CSP) uniformly at random. The main idea is to transform the constraint network into a belief network that expresses a uniform random distribution over its set of solutions and then use known sampling algorithms over belief networks. The motivation for this tasks comes from hardware verification. Random test program generation for hardware verification can be modeled and performed through CSP techniques, and is an application in which uniform random solution sampling is required.
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