Papers by Shamsiah Suhaili
2008 International Symposium on Information Technology, 2008
... Many fast adders exist, but adding fast using low area is still challenging. ... The selected... more ... Many fast adders exist, but adding fast using low area is still challenging. ... The selected adder depends on the area and timing of the implementation which influences the cost and the ... 11, both stratix and Cyclone II have higher delay and used more cells for adder design as the ...
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Journal of Signal Processing, 2017
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2020 13th International UNIMAS Engineering Conference (EnCon), 2020
A calculator is a device that can be found in daily life. This paper proposed the design of a cal... more A calculator is a device that can be found in daily life. This paper proposed the design of a calculator using Verilog HDL. A series of synthesizable Verilog code was created and simulated on Quartus II 15.0. The design of an 8-bit calculator can solve mathematical operations such as addition, subtraction, multiplication, division, square and cube functions, square root and factorial. This calculator consists of eight-digit numbers. In this paper, among the family devices in Altera, Cyclone V was used to perform the simulation process. The outputs are shown in the RTL viewer and waveform simulation of the calculator design. The implementation of a calculator was successfully designed using Verilog HDL in terms of digit numbers and the operation of the calculator function.
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ARPN journal of engineering and applied sciences, 2016
Hash Function is widely used in the protocol scheme. In this paper, the design of SHA-1 hash func... more Hash Function is widely used in the protocol scheme. In this paper, the design of SHA-1 hash function by using Verilog HDL based on FPGA is studied to optimise both hardware resource and performance. It was successfully synthesised and implemented using Altera Quartus II Arria II GX: EP2AGX45DF29C4. In this paper, two types of design are proposed, namely SHA-1 and SHA-1unfolding. The maximum frequency of SHA-1 design is 274.2 MHz which is higher than SHA-1 unfolding that has the maximum frequency of only 174.73 MHz. However, this leads to a high throughput of the SHA1 unfolding design with 2236.54 Mbps. Besides, both designs provide a small area implementation on Arria II that requires only 423 and 548 Combinational ALUTs, 693 and 907 total register, respectively
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In recent years, designing of SHA-1 hash function has become popular because it was important in ... more In recent years, designing of SHA-1 hash function has become popular because it was important in security design application. One of the applications of SHA-1 hash function was HMAC where the architecture of SHA-1 needed to be improved in terms of speed and throughput in order to obtain the high-performance design. The objective of this project was to design high speed and throughput evaluation of SHA-1 hash function based on a combination of pipelining and unfolding techniques. By using both techniques in designing the architecture of SHA-1 design, the speed of SHA-1 hash function can be increased significantly as well as throughput of the design. In this paper, five proposed SHA-1 architectures were designed with different stages of pipelining such as 1, 4 and 40 stages. The results showed the high-speed design of SHA-1 design can be obtained by using 40 stages pipelining with unfolding factor two. This design provided a high-speed implementation with maximum frequency of 308.17 M...
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Advanced Science Letters
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Papers by Shamsiah Suhaili