Proceedings of the 34th annual conference on Design automation conference - DAC '97, 1997
Novel test bench techniques are required to cope with a functional test complexity which is predi... more Novel test bench techniques are required to cope with a functional test complexity which is predicted to grow much more strongly than design complexity. Our test bench approach attacks this complexity by using a strong hierarchical architecture, application domain-independent synchronization, reusable modules, and easy incremental extendability based on table-driven techniques. In addition, the integration of VHDL/C co-simulation under the control of the test bench makes it possible to use the hardware model for software testing and vice versa and thus enables extreme reductions in test bench coding. The efficiency of our test bench has already been demonstrated in several industrial projects, among them a four-ASIC ATM board with one embedded core and one external micro controller.
This paper presents a novel TLM verification approach utilizing TLM+ as a reference model and pro... more This paper presents a novel TLM verification approach utilizing TLM+ as a reference model and providing a systematic path to RTL simulation as well. The approach is based on SystemC only but follows the established structure on an OVM testbench. Industrial relevant aspects as use of standards, early verification, and re-use of design items are established in this way.
2007 Design, Automation & Test in Europe Conference & Exhibition, 2007
In recent years other verification features than simulation performance such as robustness and de... more In recent years other verification features than simulation performance such as robustness and debugging gained increasing impact on simulation language and tool selection. However, fastest model execution speed is still priority number one for many design and verification engineers. This can be seen in the continuously growing interest in virtual prototypes and transaction level modeling (TLM).
We present a template based approach for modeling monitors in VHDL with the intention to show a f... more We present a template based approach for modeling monitors in VHDL with the intention to show a flexible VHDL system level modeling method. First an overview over existing approaches is given and the monitor approach is motivated. Second general software and VHDL aspects are discussed. Subsequent an application modeling of monitors in VHDL is shown. Finally we outlook towards protected Ada types, which have similar behavior as the planned VHDL shared variables.
Proceeding of Design and Verification Conference (DVCON), Mar 1, 2012
Abstract—This paper introduces the System Verification Methodology (SVM) Library as an advanced T... more Abstract—This paper introduces the System Verification Methodology (SVM) Library as an advanced TLM library for SystemC, which is based on the OVM-SC library, a SystemC implementation of an Open Verification Methodology (OVM) subset. SVM integrates with a functional coverage library and comes as a significant extension of the OVM-SC library, by providing domain specific components (drivers, monitors, scoreboards and others) and facilities for generation and management of stimuli. Keywords-SystemC; OVM; UVM; ...
Proceedings of the 40th conference on Design automation - DAC '03, 2003
This paper presents a new technology that accelerates functional system verification. Starting wi... more This paper presents a new technology that accelerates functional system verification. Starting with a behavioral testbench, we developed a seamless flow to generate a re-use-oriented architecture for a synthesizable testbench without losing compatibility with the original testbench. Consequently, we combine the flexibility of a behavioral testbench and the simulation performance of a synthesizable testbench, while greatly reducing the modeling overhead.
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), 2010
As pointed out in the ITRS roadmap, the level of embedded software complexity is greater than the... more As pointed out in the ITRS roadmap, the level of embedded software complexity is greater than the pure HW complexity of SoCs when comparing, for example, lines of HDL and C code. Even worse, SW complexity grows faster than HW complexity (Moore's Law) and SW productivity increases more slowly than HW productivity. A new design gap -the gap of embedded softwareas appeared.
ABSTRACT As pointed out in the ITRS roadmap, the level of embedded software complexity is greater... more ABSTRACT As pointed out in the ITRS roadmap, the level of embedded software complexity is greater than the pure HW complexity of SoCs when comparing, for example, lines of HDL and C code. Even worse, SW complexity grows faster than HW complexity (Moore's Law) and SW productivity increases more slowly than HW productivity. A new design gap - the gap of embedded software -- as appeared. EDA has now identified ESL as a field with sufficient revenue and revenue growth, but do they really approach the SW productivity challenge? This panel gives the answer by presenting recent EDS products and solutions in the area of ESW, contrasting them with needs of industry, and discussing ways out of the ESL productivity crisis.
This paper describes an approach for VHDL-based communication and synchronization synthesis. This... more This paper describes an approach for VHDL-based communication and synchronization synthesis. This design step transforms a system level VHDL description into an RT-level description. The idea is, not to synthesize system level implementations of communication and synchronization mechanisms but to perform the synthesis step as a mapping step of an abstract communication or synchronization mechanism to one of a set of RT-level implementations.
This article presents methods for the verification of RT-Level subroutines. Special emphasis lies... more This article presents methods for the verification of RT-Level subroutines. Special emphasis lies on subroutines and operators of the VHDL standard synthesis packages, which are currently in the ballot phase. The methods are VHDL based only. Therefore they can be used for both verification of the synthesis package on different VHDL simulators and tests of simulator-built-in implementations of the package.
Functional test environments become more and more important for the design of complex application... more Functional test environments become more and more important for the design of complex applications and systems. A lot of approaches show the integration of Hardware/Software Cosimulation in those environments. Another focus is the reuse of ...
Proceedings of the conference on Design, automation and test in Europe - DATE '08, 2008
Abstract Effective integration of advanced systems-on-chip (SoC) requires extensive reuse of IP m... more Abstract Effective integration of advanced systems-on-chip (SoC) requires extensive reuse of IP modules as well as automation of the IP integration process, including verification. Key enablers for this are standards to describe and package IP modules. We focus on the IP-...
Proceedings of the 34th annual conference on Design automation conference - DAC '97, 1997
Novel test bench techniques are required to cope with a functional test complexity which is predi... more Novel test bench techniques are required to cope with a functional test complexity which is predicted to grow much more strongly than design complexity. Our test bench approach attacks this complexity by using a strong hierarchical architecture, application domain-independent synchronization, reusable modules, and easy incremental extendability based on table-driven techniques. In addition, the integration of VHDL/C co-simulation under the control of the test bench makes it possible to use the hardware model for software testing and vice versa and thus enables extreme reductions in test bench coding. The efficiency of our test bench has already been demonstrated in several industrial projects, among them a four-ASIC ATM board with one embedded core and one external micro controller.
This paper presents a novel TLM verification approach utilizing TLM+ as a reference model and pro... more This paper presents a novel TLM verification approach utilizing TLM+ as a reference model and providing a systematic path to RTL simulation as well. The approach is based on SystemC only but follows the established structure on an OVM testbench. Industrial relevant aspects as use of standards, early verification, and re-use of design items are established in this way.
2007 Design, Automation & Test in Europe Conference & Exhibition, 2007
In recent years other verification features than simulation performance such as robustness and de... more In recent years other verification features than simulation performance such as robustness and debugging gained increasing impact on simulation language and tool selection. However, fastest model execution speed is still priority number one for many design and verification engineers. This can be seen in the continuously growing interest in virtual prototypes and transaction level modeling (TLM).
We present a template based approach for modeling monitors in VHDL with the intention to show a f... more We present a template based approach for modeling monitors in VHDL with the intention to show a flexible VHDL system level modeling method. First an overview over existing approaches is given and the monitor approach is motivated. Second general software and VHDL aspects are discussed. Subsequent an application modeling of monitors in VHDL is shown. Finally we outlook towards protected Ada types, which have similar behavior as the planned VHDL shared variables.
Proceeding of Design and Verification Conference (DVCON), Mar 1, 2012
Abstract—This paper introduces the System Verification Methodology (SVM) Library as an advanced T... more Abstract—This paper introduces the System Verification Methodology (SVM) Library as an advanced TLM library for SystemC, which is based on the OVM-SC library, a SystemC implementation of an Open Verification Methodology (OVM) subset. SVM integrates with a functional coverage library and comes as a significant extension of the OVM-SC library, by providing domain specific components (drivers, monitors, scoreboards and others) and facilities for generation and management of stimuli. Keywords-SystemC; OVM; UVM; ...
Proceedings of the 40th conference on Design automation - DAC '03, 2003
This paper presents a new technology that accelerates functional system verification. Starting wi... more This paper presents a new technology that accelerates functional system verification. Starting with a behavioral testbench, we developed a seamless flow to generate a re-use-oriented architecture for a synthesizable testbench without losing compatibility with the original testbench. Consequently, we combine the flexibility of a behavioral testbench and the simulation performance of a synthesizable testbench, while greatly reducing the modeling overhead.
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), 2010
As pointed out in the ITRS roadmap, the level of embedded software complexity is greater than the... more As pointed out in the ITRS roadmap, the level of embedded software complexity is greater than the pure HW complexity of SoCs when comparing, for example, lines of HDL and C code. Even worse, SW complexity grows faster than HW complexity (Moore's Law) and SW productivity increases more slowly than HW productivity. A new design gap -the gap of embedded softwareas appeared.
ABSTRACT As pointed out in the ITRS roadmap, the level of embedded software complexity is greater... more ABSTRACT As pointed out in the ITRS roadmap, the level of embedded software complexity is greater than the pure HW complexity of SoCs when comparing, for example, lines of HDL and C code. Even worse, SW complexity grows faster than HW complexity (Moore's Law) and SW productivity increases more slowly than HW productivity. A new design gap - the gap of embedded software -- as appeared. EDA has now identified ESL as a field with sufficient revenue and revenue growth, but do they really approach the SW productivity challenge? This panel gives the answer by presenting recent EDS products and solutions in the area of ESW, contrasting them with needs of industry, and discussing ways out of the ESL productivity crisis.
This paper describes an approach for VHDL-based communication and synchronization synthesis. This... more This paper describes an approach for VHDL-based communication and synchronization synthesis. This design step transforms a system level VHDL description into an RT-level description. The idea is, not to synthesize system level implementations of communication and synchronization mechanisms but to perform the synthesis step as a mapping step of an abstract communication or synchronization mechanism to one of a set of RT-level implementations.
This article presents methods for the verification of RT-Level subroutines. Special emphasis lies... more This article presents methods for the verification of RT-Level subroutines. Special emphasis lies on subroutines and operators of the VHDL standard synthesis packages, which are currently in the ballot phase. The methods are VHDL based only. Therefore they can be used for both verification of the synthesis package on different VHDL simulators and tests of simulator-built-in implementations of the package.
Functional test environments become more and more important for the design of complex application... more Functional test environments become more and more important for the design of complex applications and systems. A lot of approaches show the integration of Hardware/Software Cosimulation in those environments. Another focus is the reuse of ...
Proceedings of the conference on Design, automation and test in Europe - DATE '08, 2008
Abstract Effective integration of advanced systems-on-chip (SoC) requires extensive reuse of IP m... more Abstract Effective integration of advanced systems-on-chip (SoC) requires extensive reuse of IP modules as well as automation of the IP integration process, including verification. Key enablers for this are standards to describe and package IP modules. We focus on the IP-...
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Papers by Wolfgang Ecker